Zakładka z wyszukiwarką danych komponentów
  Polish  ▼

Delete All
ON OFF
ALLDATASHEET.PL

X  

Preview PDF Download HTML

AD1833A Arkusz danych(PDF) 10 Page - Analog Devices

Numer części AD1833A
Szczegółowy opis  24-Bit, 192 kHz, DAC
Download  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD1833A Arkusz danych(HTML) 10 Page - Analog Devices

Back Button AD1833A Datasheet HTML 6Page - Analog Devices AD1833A Datasheet HTML 7Page - Analog Devices AD1833A Datasheet HTML 8Page - Analog Devices AD1833A Datasheet HTML 9Page - Analog Devices AD1833A Datasheet HTML 10Page - Analog Devices AD1833A Datasheet HTML 11Page - Analog Devices AD1833A Datasheet HTML 12Page - Analog Devices AD1833A Datasheet HTML 13Page - Analog Devices AD1833A Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 20 page
background image
REV. 0
AD1833A
–10–
FUNCTIONAL DESCRIPTION
Device Architecture
The AD1833A is a six-channel audio DAC featuring multibit
sigma-delta (
S-D) technology. The AD1833A features three stereo
converters (providing six channels); each stereo channel is con-
trolled by a common bit-clock (BCLK) and synchronization
signal (L/RCLK).
General Overview
The AD1833A is designed to run with an internal MCLK
(IMCLK) of 24.576 MHz and a modulator rate of 6.144 MHz
(i.e., IMCLK/4). From this IMCLK frequency, sample rates of
48 kHz and 96 kHz can be achieved on six channels or 192 kHz
can be achieved on two channels. The internal clock should never
be run at a higher frequency but may be reduced to achieve
lower sampling rates, i.e., for a sample rate of 44.1 kHz, the appro-
priate internal MCLK is 22.5792 MHz. The modulator rate scales
in proportion with the MCLK scaling.
Interpolator
The interpolator consists of as many as three stages of sample
rate doubling and half-band filtering followed by a 16-sample
zero order hold (ZOH). The sample rate doubling is achieved
by zero stuffing the input samples, and a digital half-band filter
is used to remove any images above the band of interest and to
bring the zero samples to their correct values.
The interpolator output must always be at a rate of IMCLK/64.
Depending on the interpolation rates selected, one, two, or all
three stages of doubling may be switched in. This allows for
three different sample rate inputs for any given IMCLK. For an
IMCLK of 24.576 MHz, all three doubling stages are used with
a 48 kHz input sample rate; with a 96 kHz input sample rate, only
two doubling stages are used; and with a 192 kHz input sample
rate, only one doubling stage is used. In each case, the input
sample frequency is increased to 384 kHz (IMCLK/64). The
ZOH holds the interpolator samples for upsampling by the
modulator. This is done at a rate 16 times the interpolator
output sample rate.
Modulator
The modulator is a 6-bit, second order implementation and uses
data scrambling techniques to achieve perfect linearity. The modu-
lator samples the output of the interpolator stage(s) at a rate of
(IMCLK/4).
OPERATING FEATURES
SPI Register Definitions
The SPI port allows flexible control of the device’s programmable
functions. It is organized around nine registers: six individual channel
volume registers and three control registers. Each write operation
to the AD1833A SPI control port requires 16 bits of serial data
in MSB-first format. The four most significant bits are used to
select one of nine registers (seven register addresses are reserved),
and the bottom 10 bits are written to that register. This allows a
write to one of the nine registers in a single 16-bit transaction. The
SPI CCLK signal is used to clock in the data. The incoming
data should change on the falling edge of this signal and remain
valid during the rising edge. At the end of the 16 CCLK periods,
the CLATCH signal should rise to latch the data internally into
the AD1833A (see Figure 2).
The serial interface format used on the control port uses a 16-bit
serial word, as shown in Table I. The 16-bit word is divided into
several fields: Bits 15 through 12 define the register address, Bits 11
and 10 are reserved and must be programmed to 0, and Bits 9
through 0 are the data field (which has specific definitions,
depending on the register selected).
Table I. Control Port Map
Register Address
Reserved
1
Data Field
15
2
14
13
12
11
10
9876543210
NOTES
1Must be programmed to zero.
2Bit 15 = MSB.
Bit 15
Bit 14
Bit 13
Bit 12
Register Function
00
00
DAC Control 1
00
01
DAC Control 2
00
10
DAC Volume 1
00
11
DAC Volume 2
01
00
DAC Volume 3
01
01
DAC Volume 4
01
10
DAC Volume 5
01
11
DAC Volume 6
10
00
DAC Control 3
10
01
Reserved
10
10
Reserved
10
11
Reserved
11
00
Reserved
11
01
Reserved
11
10
Reserved
11
11
Reserved


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20 


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn