AD1833A datasheet(14/20 Pages) AD

Numer części	AD1833A

Szczegółowy opis	24-Bit, 192 kHz, DAC

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Producent	AD [Analog Devices]

Strona internetowa	http://www.analog.com

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14 / 20 page

REV. 0

AD1833A

–14–

I

2S Timing

I

2S timing uses an

L/RCLK to define when the data being trans-

mitted is for the left channel and when it is for the right channel.

The

L/RCLK is low for the left channel and high for the right

channel. A bit clock running at 64

fS is used to clock in the data.

There is a delay of 1 bit clock from the time the

L/RCLK signal

changes state to the first bit of data on the SDINx lines. The data

is written MSB first and is valid on the rising edge of the bit clock.

Left-Justified Timing

Left-justified (LJ) timing uses an L/

RCLK to define when the

data being transmitted is for the left channel and when it is for

the right channel. The L/

RCLK is high for the left channel and

low for the right channel. A bit clock running at 64

fS is used

LEFT CHANNEL

RIGHT CHANNEL

LSB

+1

LSB

MSB

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

LSB

+2

MSB

–2

MSB

–1

MSB

LSB

+1

LSB

+2

MSB

–2

MSB

–1

MSB

Figure 6. I 2S Timing Diagram

LEFT CHANNEL

RIGHT CHANNEL

LSB

+1

LSB

L/RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

LSB

+2

MSB

–2

MSB

–1

MSB

LSB

+1

LSB

+2

MSB

–2

MSB

–1

MSB

–1

MSB

Figure 7. Left-Justified Timing Diagram

LEFT CHANNEL

RIGHT CHANNEL

LSB

+1

LSB

L/

RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

LSB

+2

MSB

–2

MSB

–1

LSB

MSB

LSB

+1

LSB

+2

MSB

–2

MSB

–1

MSB

Figure 8. Right-Justified Timing Diagram

to clock in the data. The first bit of data appears on the SDINx

lines when the L/

RCLK toggles. The data is written MSB first

and is valid on the rising edge of the bit clock.

Right-Justified Timing

Right-justified (RJ) timing uses an L/

RCLK to define when the

data being transmitted is for the left channel and when it is for

the right channel. The L/

RCLK is high for the left channel and

low for the right channel. A bit clock running at 64

fS is used

to clock in the data. The first bit of data appears on the SDINx

8-bit clock periods (for 24-bit data) after L/

RCLK toggles. In RJ

mode, the LSB of data is always clocked by the last bit clock

before L/

RCLK transitions. The data is written MSB first and is

valid on the rising edge of the bit clock.

Podobny numer części - AD1833A

Producent	Numer części	Arkusz danych	Szczegółowy opis
Analog Devices	AD1833AST	419Kb / 20P	Multichannel 24-Bit, 192 kHz, DAC REV. 0
Analog Devices	AD1833A	697Kb / 20P	Multichannel, 24-Bit, 192 kHz, DAC REV. 0

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Podobny opis - AD1833A

Producent	Numer części	Arkusz danych	Szczegółowy opis
Analog Devices	AD1833	532Kb / 20P	Multichannel, 24-Bit, 192 kHz, DAC REV. A
	AD1833A	697Kb / 20P	Multichannel, 24-Bit, 192 kHz, DAC REV. 0
	AD1833	419Kb / 20P	Multichannel 24-Bit, 192 kHz, DAC REV. 0
Asahi Kasei Microsystem...	AK4359	369Kb / 32P	192 KHZ 24 BIT 8CH DAC
Wolfson Microelectronic...	WM8727	180Kb / 16P	24 BIT 192 KHZ STEREO DAC
Analog Devices	AD1853	416Kb / 16P	Stereo, 24-Bit, 192 kHz, Multibit DAC REV. A
	AD1852	234Kb / 16P	Stereo, 24-Bit, 192 kHz Multibit DAC REV. 0
	AD1853JRSZ	358Kb / 16P	Stereo, 24-Bit, 192 kHz, Multibit DAC REV. A
	AD1853	358Kb / 16P	Stereo, 24-Bit, 192 kHz, Multibit DAC REV. A
Cirrus Logic	CS4340A	695Kb / 21P	24-Bit, 192 kHz Stereo DAC for Audio

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