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AD1833A Arkusz danych(PDF) 14 Page - Analog Devices |
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AD1833A Arkusz danych(HTML) 14 Page - Analog Devices |
14 / 20 page REV. 0 AD1833A –14– I 2S Timing I 2S timing uses an L/RCLK to define when the data being trans- mitted is for the left channel and when it is for the right channel. The L/RCLK is low for the left channel and high for the right channel. A bit clock running at 64 fS is used to clock in the data. There is a delay of 1 bit clock from the time the L/RCLK signal changes state to the first bit of data on the SDINx lines. The data is written MSB first and is valid on the rising edge of the bit clock. Left-Justified Timing Left-justified (LJ) timing uses an L/ RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/ RCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used LEFT CHANNEL RIGHT CHANNEL LSB +1 LSB MSB L/RCLK INPUT BCLK INPUT SDATA INPUT LSB +2 MSB –2 MSB –1 MSB LSB +1 LSB LSB +2 MSB –2 MSB –1 MSB Figure 6. I 2S Timing Diagram LEFT CHANNEL RIGHT CHANNEL LSB +1 LSB L/RCLK INPUT BCLK INPUT SDATA INPUT LSB +2 MSB –2 MSB –1 MSB LSB +1 LSB LSB +2 MSB –2 MSB –1 MSB MSB –1 MSB Figure 7. Left-Justified Timing Diagram LEFT CHANNEL RIGHT CHANNEL LSB +1 LSB L/ RCLK INPUT BCLK INPUT SDATA INPUT LSB +2 MSB –2 MSB –1 LSB MSB LSB +1 LSB LSB +2 MSB –2 MSB –1 MSB Figure 8. Right-Justified Timing Diagram to clock in the data. The first bit of data appears on the SDINx lines when the L/ RCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. Right-Justified Timing Right-justified (RJ) timing uses an L/ RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/ RCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used to clock in the data. The first bit of data appears on the SDINx 8-bit clock periods (for 24-bit data) after L/ RCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before L/ RCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. |
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