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AD1833A Arkusz danych(PDF) 3 Page - Analog Devices

Numer części AD1833A
Szczegółowy opis  24-Bit, 192 kHz, DAC
Download  20 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD1833A Arkusz danych(HTML) 3 Page - Analog Devices

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REV. 0
–3–
AD1833A
Parameter
Min
Typ
Max
Unit
Test Conditions
DIGITAL I/O
Input Voltage HI
2.4
V
Input Voltage LO
0.8
V
Output Voltage HI
DVDD2 – 0.4
V
Output Voltage LO
0.4
V
POWER SUPPLIES
Supply Voltage (AVDD and DVDD1)
4.5
5
5.5
V
Supply Voltage (DVDD2)
3.3
DVDD1 V
Supply Current IANALOG
38.5
42
mA
Supply Current IDIGITAL
42
48
mA
Active
2mA
Power-Down
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
–60
dB
20 kHz 300 mV p-p Signal at Analog Supply Pins
–50
dB
Specifications subject to change without notice.
DIGITAL TIMING
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tML
MCLK LO (All Modes)
*
15
ns
24 MHz clock, clock doubler bypassed
tMH
MCLK HI (All Modes)
*
15
ns
24 MHz clock, clock doubler bypassed
tPDR
PD/RST LO
20
ns
SPI PORT
tCCH
CCLK HI Pulsewidth
20
ns
tCCL
CCLK LO Pulsewidth
20
ns
tCCP
CCLK Period
80
ns
tCDS
CDATA Setup Time
10
ns
To CCLK rising
tCDH
CDATA Hold Time
10
ns
From CCLK rising
tCLS
CLATCH Setup
10
ns
To CCLK rising
tCLH
CLATCH Hold
10
ns
From CCLK rising
DAC SERIAL PORT
tDBH
BCLK HI
15
ns
tDBL
BCLK LO
15
ns
tDLS
L/RCLK Setup
10
ns
To BCLK rising
tDLH
L/RCLK Hold
10
ns
From BCLK rising
tDDS
SDATA Setup
10
ns
To BCLK rising
tDDH
SDATA Hold
15
ns
From BCLK rising
TDM MODE MASTER
tTMBD
BCLKTDM Delay
20
ns
From MCLK rising
tTMFSD
FSTDM Delay
10
ns
From BCLKTDM rising
tTMDDS
SDIN1 Setup
15
ns
To BCLKTDM falling
tTMDDH
SDIN1 Hold
15
ns
From BCLKTDM falling
TDM MODE SLAVE
fTSB
BCLKTDM Frequency
256
fS
tTSBCH
BCLKTDM High
20
ns
tTSBCL
BCLKTDM Low
20
ns
tTSFS
FSTDM Setup
10
ns
To BCLKTDM falling
tTSFH
FSTDM Hold
10
ns
From BCLKTDM falling
tTSDDS
SDIN1 Setup
15
ns
To BCLKTDM falling
tTSDDH
SDIN1 Hold
15
ns
From BCLKTDM falling
AUXILIARY INTERFACE
tAXLRD
L/RCLK Delay
10
ns
From BCLK falling
tAXDD
Data Delay
10
ns
From BCLK falling
tAXBD
AUXBCLK Delay
20
ns
From MCLK rising
*MCLK symmetry must be better than 60:40 or 40:60.
Specifications subject to change without notice.
(Guaranteed over –40 C to +85 C, AVDD = DVDD = 5 V
10%)


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