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TP3404V Arkusz danych(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części TP3404V
Szczegółowy opis  Quad Digital Adapter for Subscriber Loops (QDASL)
Download  14 Pages
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP3404V Arkusz danych(HTML) 7 Page - National Semiconductor (TI)

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Functional Description (Continued)
ACTIVATION AND LOOP SYNCHRONIZATION
Activation (ie power-up and loop synchronization) may be
initiated from either end of the loop If the master (QDASL)
end is activating the loop it sends normal bursts of scram-
bled ‘‘1’’s which are detected by the slave’s line-signal-de-
tect circuitry The slave then replies with bursts of scram-
bled ‘‘1’’s synchronized to the received bursts and the
Framing Detection circuit at each end searches for 4 con-
secutive correctly formatted receive bursts to acquire full
loop synchronization The QDASL receiver indicates when it
is correctly in sync with received bursts by setting an indica-
tion in the Status Register and pulling the INT pin low
For the slave end to initiate activation it begins transmission
of alternate bursts ie the burst repetition rate is 2 KHz not
4 KHz At this point the slave is running from its local oscilla-
tor and is not receiving any sync information from the mas-
ter When the master’s Line-Signal Detect Circuit recogniz-
es this ‘‘wake-up’’ signal the appropriate QDASL line must
be activated by writing to the Control Register The master
begins to transmit bursts synchronized as normal to the FS
input with a 4 KHz repetition rate This enables the slave’s
receiver to correctly identify burst timing from the master
and to re-synchronize its own burst transmissions to those it
receives The Framing Detection Circuits then acquire full
loop sync as described earlier
Loop synchronization is considered to be lost if the Framing
Detection Circuit does not find four framing marks of the
four consecutive 4 KHz line frames At this point an indica-
tion is set in the Status Register the INT output is pulled
low and the receiver searches to re-acquire loop sync
MICROWIRE CONTROL INTERFACE
A serial interface which can be clocked independently from
the B and D channel system interfaces is provided for mi-
crocontroller access to the time-slot assignment Control
and Status Registers in the QDASL The microcontroller is
normally the timing master of this interface and it supplies
the CCLK and CS signals
All data transfers consist of simultaneous read and write
cycles in which 2 continuous bytes are sampled on the CI
pin at the same time as 2 bytes are shifted out from the CO
pin see
Figure 6 The first byte is a register address and the
second is the data To initiate a Microwire readwrite cycle
CS must be pulled low for 16 cycles of CCLK Data on CI is
sampled on rising edges of CCLK and shifted out from CO
on failing edges When CS is high the CO pin is in the high-
impedance TRI-STATE enabling the CO pins of many de-
vices to be multiplexed together
Whenever a change (except Bipolar Violation) in any of the
QDASL status conditions occurs the Interrupt output INT is
pulled low to alert the microprocessor to initiate a read cycle
of the Status Register This latched output is cleared when
the read cycle is initiated
Table 1 lists the address map of control functions and
status indicators Table 2 lists the addresses for the Control
Registers for each QDASL line Even-numbered addresses
are read-write cycles in which the data returned by the CO
pin is previous contents of the addressed register Odd-
numbered addresses are readback commands only
TABLE I Global Register Address Map
Address
Registers
(Hex)
00 – 0F
LINE 0 Control (TSXTSRCTRL)
10 – 1F
LINE 1 Control (TSXTSRCTRL)
20 – 2F
LINE 2 Control (TSXTSRCTRL)
30 – 3F
LINE 3 Control (TSXTSRCTRL)
40 – CF
Not used
FF
Common Status Register for all lines (0 – 3)
See Table VI
TABLE II Per Line Control Register Address Map
Function
Byte 1
(Note 2)
Byte 2
MSB Nibble
LSB Nibble
(Note 1)
7
6543210
Write TSXD Register
N
0
0
0
0
See Table V
Read TSXD Register
N
0
0
0
1
See Table V
Write TSXB1 Register
N
0
0
1
0
See Table IV
Read TSXB1 Register
N
0
0
1
1
See Table IV
Write TSXB2 Register
N
0
1
0
0
See Table IV
Read TSXB2 Register
N
0
1
0
1
See Table IV
Write TSRD Register
N
0
1
1
0
See Table V
Read TSRD Register
N
0
1
1
1
See Table V
Write TSRB1 Register
N
1
0
0
0
See Table IV
Read TSRB1 Register
N
1
0
0
1
See Table IV
Write TSRB2 Register
N
1
0
1
0
See Table IV
Read TSRB2 Register
N
1
0
1
1
See Table IV
Write Line Control Register (CTR L)
N
1
1
1
0
See Table III
Read Line Control Register (CTRL)
N
1
1
1
1
See Table III
Note 1
N e 0 1 2 or 3 in straight Binary notation for Line 0 1 2 or 3 respectively
Note 2
Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI and CO pins
7


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