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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADC12DJ3200AAVT Arkusz danych(PDF) 4 Page - Texas Instruments |
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ADC12DJ3200AAVT Arkusz danych(HTML) 4 Page - Texas Instruments |
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4 / 111 page  4 ADC12DJ3200 SLVSD97 – MAY 2017 www.ti.com Product Folder Links: ADC12DJ3200 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTION NAME NO. AGND A1, A2, A3, A6, A7, B2, B3, B4, B5, B6, B7, C6, D1, D6, E1, E6, F2, F3, F6, G2, G3, G6, H1, H6, J1, J6, L2, L3, L4, L5, L6, L7, M1, M2, M3, M6, M7 — Analog supply ground. AGND and DGND should be tied to a common ground plane (GND) on circuit board. DGND A12, B12, D9, D10, F9, F10, G9, G10, J9, J10, L12, M12 — Digital supply ground. AGND and DGND should be tied to a common ground plane (GND) on circuit board. BG C3 O Bandgap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads as specified in Recommended Operating Conditions. This pin can be left disconnected if not used. CALSTAT F7 O Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used. CALTRIG E7 I Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. This pin should be tied to GND if not used. CLK+ F1 I Device (sampling) clock positive input. The clock signal is strongly recommended to be AC coupled to this input for best performance. In single channel mode, the analog input signal is sampled on both rising and falling edges. In dual channel mode, the analog signal is sampled on the rising edge. This differential input has an internal 100-Ω differential termination and is self-biased to the optimal input common mode voltage as long as DEVCLK_LVPECL_EN is set to 0. CLK- G1 I Device (sampling) clock negative input. Must be AC coupled. DA0+ E12 O High-speed serialized-data output for channel A, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. DA0- F12 O High-speed serialized-data output for channel A, lane 0, negative connection. This pin can be left disconnected if not used. DA1+ C12 O High-speed serialized-data output for channel A, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. DA1- D12 O High-speed serialized-data output for channel A, lane 1, negative connection. This pin can be left disconnected if not used. DA2+ A10 O High-speed serialized-data output for channel A, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. DA2- A11 O High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left disconnected if not used. DA3+ A8 O High-speed serialized-data output for channel A, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. DA3- A9 O High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left disconnected if not used. DA4+ E11 O High-speed serialized-data output for channel A, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. DA4- F11 O High-speed serialized-data output for channel A, lane 4, negative connection. This pin can be left disconnected if not used. |
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