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ADC12DJ3200AAVT Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADC12DJ3200AAVT Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 111 page 9 ADC12DJ3200 www.ti.com SLVSD97 – MAY 2017 Product Folder Links: ADC12DJ3200 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Measured to AGND. (2) Measured to DGND. (3) It is strongly recommended that CLK+/– be AC coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK+/– to self bias to the optimal input common mode voltage for best performnace. TI recommends AC coupling for SYSREF+/– unless DC coupling is required, in which case LVPECL input mode must be used (SYSREF_LVPECL_EN = 1). (4) TMSTP+/– does not have internal biasing which requires TMSTP+/– to be biased externally whether AC coupled with TMSTP_LVPECL_EN = 0 or DC coupled with TMSTP_LVPECL_EN = 1. (5) ADC output code will saturate when VID for INA+/– or INB+/– exceeds the programmed full-scale voltage (VFS) set by FS_RANGE_A for INA+/– or FS_RANGE_B for INB+/–. (6) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate. (7) Tested up to 1000 hours continuous operation at Tj = 125°C. See Absolute Maximum Ratings for absolute maximum operational temperature. 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply Voltage Range VA19, Analog 1.9V supply(1) 1.8 1.9 2.0 V VA11, Analog 1.1V supply(1) 1.05 1.1 1.15 V VD11, Digital 1.1V supply(2) 1.05 1.1 1.15 V VCMI Input common mode voltage INA+, INA–, INB+, INB–(1) -50 0 100 mV CLK+, CLK–, SYSREF+, SYSREF–(1)(3) 0.0 0.3 0.55 V TMSTP+, TMSTP–(1)(4) 0.0 0.3 0.55 V VID Input voltage, peak-to-peak differential CLK+ to CLK–, SYSREF+ to SYSREF–, TMSTP+ to TMSTP– 0.4 1.0 2.0 VPP-DIFF INA+ to INA–, INB+ to INB– 1.0(5) VPP-DIFF VIH High level input voltage CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, PD, SCLK, SCS, SDI, SYNCSE(1) 0.7 V VIL Low level input voltage CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, PD, SCLK, SCS, SDI, SYNCSE(1) 0.45 V IC_TD Temperature diode input current TDIODE+ to TDIODE– 100 µA CL BG max load capacitance 50 pF IO BG max output current 100 µA DC Input clock duty cycle 30 50 70 % TA Operating free-air temperature -40 85 ºC Tj Operating junction temperature 105(6)(7) ºC |
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