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ADC32RF42 Arkusz danych(PDF) 4 Page - Texas Instruments

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Numer części ADC32RF42
Szczegółowy opis  Dual-Channel, 14-Bit, 1.5-GSPS, Analog-to-Digital Converter
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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ADC32RF42 Arkusz danych(HTML) 4 Page - Texas Instruments

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ADC32RF42
SBAS844 – MAY 2017
www.ti.com
Product Folder Links: ADC32RF42
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Pin Functions
NAME
NO.
I/O
DESCRIPTION
INPUT, REFERENCE
INAM
41
I
Differential analog input for channel A
INAP
42
INBM
14
I
Differential analog input for channel B
INBP
13
CM
22
O
Common-mode voltage for analog inputs, 1.2 V
CLOCK, SYNC
CLKINM
28
I
Differential clock input for the analog-to-digital converter (ADC).
This pin has an internal differential 100-Ω termination.
CLKINP
27
SYSREFM
34
I
External sync input. This pin has an internal, differential 100-Ω termination and requires external
biasing.
SYSREFP
33
GPIO1
19
I/O
GPIO control pin; configured through the SPI. This pin can be configured to be either a fast
overrange output for channel A and B, a fast detect alarm signal from the peak power detect, or
a numerically-controlled oscillator (NCO) control.
GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input.
GPIO2
20
GPIO3
21
GPIO4
63
CONTROL, SERIAL
RESET
48
I
Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
SCLK
6
I
Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor.
SDIN
5
I/O
Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN can be data
input in 4-wire mode, data input and output in 3-wire mode.
SEN
7
I
Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD.
SDOUT
11
O
Serial interface data output in 4-wire mode
PDN
50
I
Power down; active high. This pin can be configured through an SPI register setting and can be
configured to a fast overrange output channel B through the SPI.
This pin has an internal 20-kΩ pulldown resistor.
DATA INTERFACE
DA0M
62
O
JESD204B serial data output for channel A
DA0P
61
DA1M
59
DA1P
58
DA2M
56
DA2P
55
DA3M
54
DA3P
53
DB0M
65
O
JESD204B serial data output for channel B
DB0P
66
DB1M
68
DB1P
69
DB2M
71
DB2P
72
DB3M
1
DB3P
2
SYNCBM
36
I
Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic input, an
optional on-chip 100-Ω termination, and is selectable through the SPI.
This pin requires external biasing.
SYNCBP
35
POWER SUPPLY
AVDD19
10, 16, 24, 31, 39, 45
I
Analog 1.9-V power supply
AVDD
9, 12, 15, 17, 25, 30, 38,
40, 43, 44, 46
I
Analog 1.15-V power supply
DVDD
4, 8, 47, 51, 57, 64, 70
I
Digital 1.15 V-power supply, including the JESD204B transmitter
GND
3, 18, 23, 26, 29, 32, 37,
49, 52, 60, 67
I
Ground; shorted to thermal pad inside device


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