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CDCVF2505 Arkusz danych(PDF) 9 Page - Texas Instruments

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Numer części CDCVF2505
Szczegółowy opis  3.3-V Clock Phase-Lock Loop Clock Driver
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Strona internetowa  http://www.ti.com
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CDCVF2505 Arkusz danych(HTML) 9 Page - Texas Instruments

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CDCVF2505
www.ti.com
SCAS640G – JULY 2000 – REVISED AUGUST 2016
Product Folder Links: CDCVF2505
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Copyright © 2000–2016, Texas Instruments Incorporated
9.4 Device Functional Modes
The device has two functional modes: active and power down.
The CDCVF2505 automatically switches from active to power down, and vice versa, when the detected CLKIN
reference frequency is low. The PLL automatically switches on and tries to lock to the reference clock as soon as
the input frequency exceeds 20 MHz (typical). The PLL switches off and tri-states the output buffers when the
input frequency goes below 12 MHz (typical).
(1)
Full device functionality is specified for frequencies equal to or higher
than 24 MHz. Below 1 MHz, the device goes in power-down mode in
which the PLL is turned off and the outputs enter into Hi-Z mode.
Table 1. Function Table
INPUT
OUTPUTS
CLKIN
1Y (0:3)
CLKOUT
L
L
L
H
H
H
≤1 MHz(1)
Z
Z


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