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GS71108ASJ-7I Arkusz danych(PDF) 5 Page - List of Unclassifed Manufacturers |
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5 / 14 page Rev: 1.04a 10/2002 5/14 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71108ATP/J/SJ/U AC Test Conditions AC Characteristics * These parameters are sampled and are not 100% tested Read Cycle Parameter Symbol -7 -8 -10 -12 Unit Min Max Min Max Min Max Min Max Read cycle time tRC 7 — 8 — 10 — 12 — ns Address access time tAA — 7 — 8 — 10 — 12 ns Chip enable access time (CE)tAC — 7 — 8 — 10 — 12 ns Output enable to output valid (OE)tOE —3— 3.5 — 4 — 5 ns Output hold from address change tOH 3—3— 3 — 3 — ns Chip enable to output in low Z (CE)tLZ*3 — 3 — 3 — 3 — ns Output enable to output in low Z (OE)tOLZ*0 — 0 — 0 — 0 — ns Chip disable to output in High Z (CE)tHZ*— 3.5 — 4 — 5 — 6 ns Output disable to output in High Z (OE)tOHZ*— 3 — 3.5 — 4 — 5 ns DQ VT = 1.4 V 50 Ω 30pF1 DQ 3.3 V Output Load 1 Output Load 2 589 Ω 434 Ω 5pF1 Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ Parameter Conditions Input high level VIH = 2.4 V Input low level VIL = 0.4 V Input rise time tr = 1 V/ns Input fall time tf = 1 V/ns Input reference level 1.4 V Output reference level 1.4 V Output load Fig. 1& 2 |
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