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AD9609-65EBZ Arkusz danych(PDF) 1 Page - Analog Devices |
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AD9609-65EBZ Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 33 page 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9609 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 61.5 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input Low power 45 mW at 20 MSPS 76 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.10 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imaging FUNCTIONAL BLOCK DIAGRAM SPI MODE CONTROLS DIVIDE BY 1 TO 8 DCS REF SELECT VIN+ VIN– VREF SENSE CLK+ CLK– AVDD GND SDIO SCLK CSB PDWN AD9609 DFS MODE D0 (LSB) DCO D9 (MSB) OR ADC CORE PROGRAMMING DATA VCM RBIAS DRVDD Figure 1. PRODUCT HIGHLIGHTS 1. The AD9609 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. 3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D9 to D0) timing and offset adjustments, and voltage reference modes. 4. The AD9609 is packaged in a 32-lead RoHS compliant LFCSP that is pin compatible with the AD9629 12-bit ADC and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS. |
Podobny numer części - AD9609-65EBZ |
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