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ADP3194JRUZ-RL Arkusz danych(PDF) 6 Page - Analog Devices |
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ADP3194JRUZ-RL Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 32 page ADP3194 Rev. 0 | Page 6 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP3194 TOP VIEW (Not to Scale) 1 2 3 28 27 26 4 8 10 12 14 5 6 7 21 24 23 22 9 11 17 18 19 13 15 16 20 25 VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 to 6 VID4 to VID0, VID5 Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing Logic 1 is left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to 1.6 V (see Table 2). Leaving all the VID pins open results in ADP3194 going into a No CPU mode, shutting off their PWM outputs and pulling the PWRGD output low. 7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. 8 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point. 9 COMP Error Amplifier Output and Compensation Point. 10 PWRGD Power Good Output. Open drain output that signals when the output voltage is outside of the proper oper- ating range. 11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 12 DELAY Soft Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time. 13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. 14 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. 15 ILIMIT Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit thresh old of the converter. This pin is actively pulled low when the ADP3194 EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. 16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power good and crowbar functions. This pin should be connected to the common point of the output inductors. 17 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 18 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the slope of the load line and the positioning loop response time. 19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground. 20 to 23 SW4 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. Leave the SW pins of unused phases open. 24 to 27 PWM4 to PMW1 Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3120A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the ADP3194 to operate as a 2-, 3-, or 4-phase controller. 28 VCC A 300 Ω resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V. |
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