Zakładka z wyszukiwarką danych komponentów |
|
AME8530AEEVAFX29 Arkusz danych(PDF) 9 Page - Analog Microelectronics |
|
AME8530AEEVAFX29 Arkusz danych(HTML) 9 Page - Analog Microelectronics |
9 / 13 page AME, Inc. 9 AME8510 / 8520 / 8530 Micropower µµµµµP Watch Dog Timer n Detailed Description The AME8510/8520/8530 are designed to interface with the reset input of a microprocessor and to prevent CPU execution errors due to power up, power down, and other power supply errors. The AME8510/8520 also monitor the CPU health by checking for signal transitions from the CPU at the WDI input. Reset Output Each output pin in the family can be configured to be either push/pull or open drain. In addition each output may be either active high or active low with the condition that parts with two outputs must have opposite polari- ties. Active high reset outputs are denoted as RESET. Active low reset outputs are denoted as RESETB. The selection guide on page 3 of this data sheet shows all possible combinations of output driver configuration. A reset will be asserted if any of three things happen: 1) V DD drops below the threshold (VTH) 2) The MRB pin is pulled low. 3) The WDI pin does not detect a transition within the watch dog interval (T WD). The reset will remain asserted for the prescribed reset interval after: 1) V DD rises above the threshold (VTH) 2) MRB goes high 3) The watch dog timer has timed out causing the reset to assert. Manual Reset Input The AME8510 and AME8530 feature a manual reset feature (MRB). A logic low on the MRB pin asserts a reset. The reset remains asserted as long as the MRB pin remains low. After the MRB pin transitions to a high state the reset remains asserted for the prescribed reset interval (T D2). The MRB pin is internally pulled up to VDD by a 100K Ω resistor. It is internally debounced to reject switching transients. The MRB pin is ESD protected by diodes connected to V DD and GND. So the MRB pin should never be driven higher than V DD or lower than GND. Watchdog Input The AME8510 and AME8520 are equipped with a watch- dog input (WDI). If the microprocessor does not produce a valid logic edge at the the watchdog input (WDI) within the prescribed watchdog interval (T WD) then a reset as- serts. The reset remains asserted for the required reset interval (T D2) At the end of the reset interval the reset is deasserted and the watchdog interval timer starts again from zero. If the watchdog input is left unconnected or is con- nected to a tri-stated buffer the watchdog function is dis- abled. As soon as the WDI input is driven either low or high the watchdog function resumes with the watchdog timer set to zero. Reset Timing Diagram WDI RESETB VDD V TH T WD T D2 T D2 Watchdog Timing Diagram V DD RESETB RESET T D2 V Release V TH T D1 T D2 T D1 50% 50% 50% 50% |
Podobny numer części - AME8530AEEVAFX29 |
|
Podobny opis - AME8530AEEVAFX29 |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |