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GS8128036GT-250V Arkusz danych(PDF) 11 Page - GSI Technology |
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GS8128036GT-250V Arkusz danych(HTML) 11 Page - GSI Technology |
11 / 23 page First Write First Read Burst Write Burst Read Deselect R W CR CW X X WR R W R X X X CR R CW CR CR W CW W CW Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. GS8128018/32/36GT-xxxV Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01 5/2017 11/22 © 2015, GSI Technology Simplified State Diagram with G |
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