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ADS114S06BIRHBR Arkusz danych(PDF) 6 Page - Texas Instruments |
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ADS114S06BIRHBR Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 88 page 6 ADS114S06B, ADS114S08B SBAS852 – AUGUST 2017 www.ti.com Product Folder Links: ADS114S06B ADS114S08B Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) AINP and AINN denote the positive and negative inputs of the PGA. Any of the available analog inputs (AINx) can be selected as either AINP or AINN by the input multiplexer. (2) VINMAX denotes the maximum differential input voltage, VIN, that is expected in the application. |VINMAX| can be smaller than VREF / Gain. (3) REFPx and REFNx denote one of the two available external differential reference input pairs. (4) An external clock is not required when the internal oscillator is used. 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY Analog power supply AVDD to AVSS 2.7 5.25 V AVSS to DGND –2.625 0 0.05 AVDD to DGND 1.5 5.25 Digital core power supply DVDD to DGND 2.7 3.6 V Digital IO power supply IOVDD to DGND DVDD 5.25 V ANALOG INPUTS(1) V(AINx) Absolute input voltage(2) PGA bypassed AVSS – 0.05 AVDD + 0.05 V PGA enabled, gain = 1 to 16 AVSS + 0.15 + |VINMAX|·(Gain – 1) / 2 AVDD – 0.15 – |VINMAX|·(Gain –1) / 2 PGA enabled, gain = 32 to 128 AVSS + 0.15 + 15.5·|VINMAX| AVDD – 0.15 – 15.5·|VINMAX| VIN Differential input voltage VIN = VAINP – VAINN –VREF / Gain VREF / Gain V VOLTAGE REFERENCE INPUTS(3) VREF Differential reference input voltage VREF = V(REFPx) – V(REFNx) 0.5 AVDD – AVSS V V(REFNx) Absolute negative reference voltage Negative reference buffer disabled AVSS – 0.05 V(REFPx) – 0.5 V Negative reference buffer enabled AVSS V(REFPx) – 0.5 V V(REFPx) Absolute positive reference voltage Positive reference buffer disabled V(REFNx) + 0.5 AVDD + 0.05 V Positive reference buffer enabled V(REFNx) + 0.5 AVDD V EXTERNAL CLOCK SOURCE(4) fCLK External clock frequency 2 4.096 4.5 MHz Duty cycle 40% 50% 60% GENERAL-PURPOSE INPUTS (GPIOs) Input voltage AVSS – 0.05 AVDD + 0.05 V DIGITAL INPUTS (Other than GPIOs) Input voltage DGND IOVDD V TEMPERATURE RANGE TA Operating ambient temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.4 Thermal Information THERMAL METRIC(1) ADS114S06B, ADS114S08B UNIT VQFN (RHB) TQFP (PBS) 32 PINS 32 PINS RθJA Junction-to-ambient thermal resistance 45.2 75.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 17.1 °C/W RθJB Junction-to-board thermal resistance 15.8 28.5 °C/W ψJT Junction-to-top characterization parameter 0.4 0.4 °C/W ψJB Junction-to-board characterization parameter 15.7 28.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 n/a °C/W |
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