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RT5509 Arkusz danych(PDF) 6 Page - Richtek Technology Corporation |
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RT5509 Arkusz danych(HTML) 6 Page - Richtek Technology Corporation |
6 / 58 page RT5509 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5509-00 August 2017 6 Parameter Symbol Test Conditions Min Typ Max Unit DAC to Stereo Speaker Amplifier Signal to Noise Ratio SNR PVDD = 9.5V, THD+N < 1%, Gain = 12dB, A-Weighting 92 100 108 dB Noise level Vn Gain = 0dB, A-Weighting 15 20 25 V Gain = 12dB, A-Weighting 35 40 45 Gain = 18dB, A-Weighting 55 60 65 Maximum Output Power Po 1kHz, PVDD = 3.6V, 8 load + 22H, THD + N = 1% 0.6 0.65 0.7 W 1kHz, PVDD = 9.5V, 8 load + 22H, THD + N = 1% 4.2 4.3 4.4 THD+N 1kHz, Po = 350mW, 8 load + 22H 90 75 50 dB PSRR 217Hz ripple = 200mVpp 85 75 65 dB Quiescent Current (VBAT) IQ_VBAT Normal operation, DSP, speaker protection bypassed 1 3 5 mA Quiescent Current (DVDD) IQ_DVDD Normal operation, DSP, speaker protection bypassed 6 12 18 mA Normal operation, DSP, speaker protection activated 12 18 24 Output Power Efficiency η PO = 2.5W, including DC to DC converter, 100Hz audio signal 70 76 80 % I 2C Interface Electrical Characteristics (Note 5) SDA, SCL Input Threshold VIH 0.7 x DVDD -- -- V VIL -- -- 0.3 x DVDD Pull-Down Current IFO2 -- 2 -- A Digital Output Low (SDA) VOL IPULLUP = 3mA -- -- 0.4 V Clock Operating Frequency fSCL -- -- 400 kHz Bus Free Time Between Stop and Start Condition tBUF 1.3 -- -- s Hold Time After (Repeated) Start Condition tHD,STA 0.6 -- -- s Repeated Start Condition Setup Time tSU,STA 0.6 -- -- s Stop Condition Time tSU,STD 0.6 -- -- s Data Hold Time tHD,DAT (OUT) 225 -- -- ns Input Data Hold Time tHD,DAT (IN) 0 -- 900 ns Data Setup Time tSU,DAT 100 -- -- ns Clock Low Period tLOW 1.3 -- -- s Clock High Period tHIGH 0.6 -- -- s |
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