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GS8180QV36BGD-167I Arkusz danych(PDF) 5 Page - GSI Technology |
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GS8180QV36BGD-167I Arkusz danych(HTML) 5 Page - GSI Technology |
5 / 28 page GS8180QV18/36BD-200/167 Rev: 1.02b 11/2011 5/28 © 2007, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half. A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand. Burst of 2 SigmaQuad SRAM DDR Read The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read cycle. Data can be clocked out one cycle later and again one half cycle after that. A high on the Read Enable-bar pin, R, begins a read port deselect cycle. Burst of 2 Double Data Rate SigmaQuad SRAM Read First Read A NOP Write B Read C Write D Read E Write F Read G Write H NOP A B C D E F G H B B+1 D D+1 F F+1 H H+1 B B+1 D D+1 F F+1 H H+1 A A+1 C C+1 E E+1 G K K Address R W BWx D C C Q |
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