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AD7761BSTZ Arkusz danych(PDF) 11 Page - Analog Devices |
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AD7761BSTZ Arkusz danych(HTML) 11 Page - Analog Devices |
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11 / 76 page  AD7761 Data Sheet Rev. A | Page 10 of 75 Parameter Test Conditions/Comments Min Typ Max Unit Low Power AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, precharge reference buffers off 65 mW AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V, precharge reference buffers on 95 mW AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 3.6 V, precharge reference buffers off 108 mW AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 1.88 V, precharge reference buffers off 94 mW Standby Mode All channels disabled; AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V 14.5 mW AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V 21 mW AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V 23.5 29 mW AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 1.88 V 12.5 mW Sleep Mode Full power-down (SPI mode only); AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V 1.8 mW AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V 2.5 mW AVDD1 = AVDD2 = 5.5 V, IOVDD = 3.6 V 2.7 6.5 mW AVDD1 = 5.5 V, AVDD2 = 5.5 V, IOVDD = 1.88 V 1.5 mW 1 The output data rate ranges refer to the programmable decimation rates available on the AD7761 for a fixed MCLK rate of 32.768 MHz. Varying MCLK rates allow users a wider variation of ODR. 2 These specifications are not production tested but are supported by characterization data at initial product release. 3 The maximum INL specification is guaranteed by design and characterization testing prior to release. This specification is not production tested. 4 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 5 −25 μA is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common-mode voltage approaches (AVDD1 − AVSS)/2. The analog input current scales with the MCLK frequency and device power mode. 6 For lower MCLK rates or higher decimation rates, use Table 25 and Table 26 to calculate any additional delay before the first DRDY pulse. 7 The RESET pin has an internal pull-up device to IOVDD. TIMING SPECIFICATIONS AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 2.25 V to 3.6 V, Input Logic 0 = DGND, Input Logic 1 = IOVDD; CLOAD = 10 pF on the DCLK pin, CLOAD = 20 pF on the other digital outputs; REFx+ = 4.096 V, TA = −40°C to +105°C. See Table 4 and Table 5 for timing specifications at 1.8 V IOVDD. Table 2. Data Interface Timing1 Parameter Description Test Conditions/Comments Min Typ Max Unit MCLK Master clock 1.15 34 MHz fMOD Modulator frequency Fast mode MCLK/4 Hz Median mode MCLK/8 Hz Low power mode MCLK/32 Hz t1 DRDY high time tDCLK = t8 + t9 tDCLK − 10% 28 ns t2 DCLK rising edge to DRDY rising edge 2 ns t3 DCLK rising to DRDY falling −3.5 0 ns t4 DCLK rise to DOUTx valid 1.5 ns t5 DCLK rise to DOUTx invalid −3 ns t6 DOUTx valid to DCLK falling 9.5 tDCLK/2 ns t7 DCLK falling edge to DOUTx invalid 9.5 tDCLK/2 ns t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns t8a = DCLK = MCLK/2 tMCLK = 1/MCLK tMCLK ns t8b = DCLK = MCLK/4 2 × tMCLK ns t8c = DCLK = MCLK/8 4 × tMCLK ns |
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