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AD9691 Arkusz danych(PDF) 8 Page - Analog Devices |
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AD9691 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 73 page Data Sheet AD9691 Rev. 0 | Page 7 of 72 Parameter Temperature Min Typ Max Unit LATENCY5 Pipeline Latency Full 55 Clock cycles Fast Detect Latency Full 28 Clock cycles Wake-Up Time6 Standby 25°C 1 ms Power-Down 25°C 4 ms APERTURE Aperture Delay (tA) Full 530 ps Aperture Uncertainty (Jitter, tj) Full 55 fs rms Out-of-Range Recovery Time Full 1 Clock cycles 1 The maximum sample rate is the clock rate after the divider. 2 The minimum sample rate operates at 300 MSPS with L = 1. 3 Baud rate = 1/UI. A subset of this range is supported by the AD9691. 4 Default L = 8. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 8, M = 2, and F = 1. 6 Wake-up time is the time required to return to normal operation from power-down mode. TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 2 tSU_SR Device clock to SYSREF+ setup time 117 ps tH_SR Device clock to SYSREF+ hold time −96 ps SPI TIMING REQUIREMENTS See Figure 3 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK signal 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns tLOW Minimum period that SCLK must be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 3) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 3) 10 ns Timing Diagrams CLK+ CLK– SYSREF+ SYSREF– tSU_SR tH_SR Figure 2. SYSREF+ Setup and Hold Timing Diagram |
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