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AD9249BBCZ-65 Arkusz danych(PDF) 1 Page - Analog Devices

Numer części AD9249BBCZ-65
Szczegółowy opis  16 Channel, 14-Bit, 65 MSPS, Serial LVDS, 1.8 V ADC
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Strona internetowa  http://www.analog.com
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16 Channel, 14-Bit,
65 MSPS, Serial LVDS, 1.8 V ADC
Data Sheet
AD9249
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Low power
16 ADC channels integrated into 1 package
58 mW per channel at 65 MSPS with scalable power options
35 mW per channel at 20 MSPS
SNR: 75 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist)
DNL: ±0.6 LSB (typical); INL: ±0.9 LSB (typical)
Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB
typical
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Flexible bit orientation
Built in and custom digital test pattern generation
Programmable clock and data alignment
Power-down and standby modes
APPLICATIONS
Medical imaging
Communications receivers
Multichannel data acquisition
GENERAL DESCRIPTION
The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low power
in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The AD9249 automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. Data clock outputs (DCO±1,
DCO±2) for capturing data on the output and frame clock outputs
(FCO±1, FCO±2) for signaling a new output byte are provided.
Individual channel power-down is supported, and the device
typically consumes less than 2 mW when all channels are disabled.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
Figure 1.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation.
The available digital test patterns include built-in deterministic
and pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9249 is available in an RoHS-compliant, 144-ball CSP-
BGA. It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Sixteen ADCs are contained in a small,
10 mm × 10 mm package.
2. Low Power. 35 mW/channel at 20 MSPS with scalable power
options.
3. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate
at frequencies of up to 455 MHz and support double data
rate (DDR) operation.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
AD9249
AVDD
PDWN
DATA
RATE
MULTIPLIER
SERIAL PORT
INTERFACE
FCO+1, FCO+2
FCO–1, FCO–2
DCO+1, DCO+2
DCO–1, DCO–2
REF
SELECT
VREF
VCM1, VCM2
1.0V
SYNC
SENSE
RBIAS1,
RBIAS2
GND CSB1,
CSB2
CLK+ CLK–
SDIO/
DFS
SCLK/
DTP
DRVDD
VIN+A1
VIN–A1
ADC
SERIAL
LVDS
D+A1
D–A1
14
VIN+A2
VIN–A2
ADC
SERIAL
LVDS
D+A2
D–A2
14
VIN+H1
VIN–H1
ADC
SERIAL
LVDS
D+H1
D–H1
14
VIN+H2
VIN–H2
ADC
SERIAL
LVDS
D+H2
D–H2
14


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