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AD9681 Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD9681
Szczegółowy opis  1.8 V Analog-to-Digital Converter
Download  41 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD9681 Arkusz danych(HTML) 8 Page - Analog Devices

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Data Sheet
AD9681
Rev. C | Page 7 of 40
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter
1, 2
Symbol
Temp
Min
Typ
Max
Unit
CLOCK3
Input Clock Rate
Full
10
1000
MHz
Conversion Rate4
Full
10
125
MSPS
Clock Pulse Width High
tEH
Full
4.00
ns
Clock Pulse Width Low
tEL
Full
4.00
ns
OUTPUT PARAMETERS3
Propagation Delay
tPD
Full
1.5
2.3
3.1
ns
Rise Time (20% to 80%)
tR
Full
300
ps
Fall Time (20% to 80%)
tF
Full
300
ps
FCO±1, FCO±2 Propagation Delay
tFCO
Full
1.5
2.3
3.1
ns
DCO±1, DCO±2 Propagation Delay5
tCPD
Full
tFCO + (tSAMPLE/16)
ns
DCO±1, DCO±2 to Data Delay5
tDATA
Full
(tSAMPLE/16) − 300
(tSAMPLE/16)
(tSAMPLE/16) + 300
ps
DCO±1, DCO±2 to FCO±1, FCO±2 Delay5
tFRAME
Full
(tSAMPLE/16) − 300
(tSAMPLE/16)
(tSAMPLE/16) + 300
ps
Lane Delay
tLD
90
ps
Data to Data Skew
tDATA-MAX − tDATA-MIN
Full
±50
±200
ps
Wake-Up Time (Standby)
25°C
250
ns
Wake-Up Time (Power-Down)6
25°C
375
μs
Pipeline Latency
Full
16
Clock
cycles
APERTURE
Aperture Delay
tA
25°C
1
ns
Aperture Uncertainty (Jitter)
tJ
25°C
135
fs rms
Out-of-Range Recovery Time
25°C
1
Clock
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Adjustable using the SPI. The conversion rate is the clock rate after the divider.
4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode.
5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fSAMPLE.
6 Wake-up time is defined as the time required to return to normal operation from power-down mode.


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