Data Sheet

AD9434

Rev. B | Page 5 of 28

DIGITAL SPECIFICATIONS

Table 3.

AD9434-370

AD9434-500

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUTS

Logic Compliance

Full

CMOS/LVDS/LVPECL

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

0.9

0.9

V

Differential Input Voltage

Full

0.2

1.8

0.2

1.8

V p-p

Full

−1.8

−0.2

−1.8

−0.2

V p-p

Full

−10

+10

−10

+10

µA

Full

−10

+10

−10

+10

µA

Input Resistance (Differential)

Full

8

10

12

8

10

12

kΩ

Input Capacitance

Full

4

4

pF

LOGIC INPUTS

Logic 1 Voltage

Full

0.8 × DRVDD

0.8 × DRVDD

V

Logic 0 Voltage

Full

0.2 × DRVDD

0.2 × DRVDD

V

Logic 1 Input Current (SDIO, CSB)

Full

0

0

µA

Logic 0 Input Current (SDIO, CSB)

Full

−60

−60

µA

Logic 1 Input Current (SCLK, PDWN)

Full

50

50

µA

Logic 0 Input Current (SCLK, PDWN)

Full

0

0

µA

Input Capacitance

25°C

4

4

pF

LOGIC OUTPUTS2

Full

247

454

247

454

mV

Full

1.125

1.375

1.125

1.375

V

Output Coding

Twos complement, Gray code, or offset binary (default)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2