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AD9266-65EBZ Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD9266-65EBZ
Szczegółowy opis  1.8 V Analog-to-Digital Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD9266
Data Sheet
Rev. B | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION ON THE DEVICE. IT MUST
BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY,
HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH.
CLK+
CLK–
AVDD
CSB
SCLK/DFS
SDIO/PDWN
DNC
DNC
AVDD
MODE/OR
DCO
(MSB) D15_D14
D13_D12
D11_D10
D9_D8
D7_D6
TOP VIEW
(Not to Scale)
AD9266
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0
EPAD
Exposed Paddle. The exposed paddle is the only ground connection on the device. It must be
soldered to the analog ground of the PCB to ensure proper functionality, heat dissipation, noise, and
mechanical strength.
1, 2
CLK+, CLK−
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32
AVDD
1.8 V Supply Pin for ADC Core Domain.
4
CSB
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
5
SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6
SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 14 for details.
7 to 12
DNC
Do Not Connect.
14 to 21
D1_D0 (LSB) to
(MSB) D15_D14
ADC Digital Outputs.
13
DRVDD
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22
DCO
Data Clock Digital Output.
23
MODE/OR
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip standby (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
25
VREF
1.0 V Voltage Reference Input/Output. See Table 10.
26
SENSE
Reference Mode Selection. See Table 10.
27
VCM
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28
RBIAS
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31
VIN−, VIN+
ADC Analog Inputs.


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