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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD9644 Arkusz danych(PDF) 10 Page - Analog Devices |
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AD9644 Arkusz danych(HTML) 10 Page - Analog Devices |
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10 / 45 page  Data Sheet AD9644 Rev. C | Page 9 of 44 TIMING SPECIFICATIONS Table 5. Parameter Conditions Limit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.30 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.30 ns typ SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns min tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns min Timing Diagrams DOUT+ SAMPLE N – 23 ENCODED INTO 2 8b/10b SYMBOLS SAMPLE N – 22 ENCODED INTO 2 8b/10b SYMBOLS SAMPLE N – 21 ENCODED INTO 2 8b/10b SYMBOLS SAMPLE N N – 22 N – 23 N – 21 N – 20 N + 1 ANALOG INPUT SIGNAL CLK+ CLK– N – 1 CLK+ CLK– DOUT– Figure 2. Data Output Timing SYNC CLK+ tHSYNC tSSYNC Figure 3. SYNC Input Timing Requirements |
Podobny numer części - AD9644_17 |
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Podobny opis - AD9644_17 |
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