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AD9648BCPZRL7-125 Arkusz danych(PDF) 4 Page - Analog Devices |
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AD9648BCPZRL7-125 Arkusz danych(HTML) 4 Page - Analog Devices |
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4 / 42 page  Data Sheet AD9648 Rev. C | Page 3 of 41 GENERAL DESCRIPTION The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on- chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus. The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). |
Podobny numer części - AD9648BCPZRL7-125 |
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Podobny opis - AD9648BCPZRL7-125 |
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