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AD9684BBPZ-500 Arkusz danych(PDF) 9 Page - Analog Devices |
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AD9684BBPZ-500 Arkusz danych(HTML) 9 Page - Analog Devices |
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9 / 65 page  AD9684 Data Sheet Parameter Temperature Min Typ Max Unit APERTURE Aperture Delay (tA) Full 530 ps Aperture Uncertainty (Jitter, tj) Full 55 fs rms Out of Range Recovery Time Full 1 Clock Cycles 1 The maximum sample rate is the clock rate after the divider. 2 The minimum sample rate operates at 300 MSPS. 3 This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes. 4 This specification is valid for byte mode output mode only. 5 No DDCs used. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode. TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit CLK± to SYNC± TIMING REQUIREMENTS See Figure 2 tSU_SR Device clock to SYNC± setup time 117 ps tH_SR Device clock to SYNC± hold time −96 ps SPI TIMING REQUIREMENTS See Figure 3 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns tLOW Minimum period that SCLK must be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 3) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 3) 10 ns Timing Diagrams CLK+ CLK– SYNC+ SYNC– tSU_SR tH_SR Figure 2. SYNC± Setup and Hold Timing DON’T CARE DON’T CARE DON’T CARE DON’T CARE SDIO SCLK tS tDH tCLK tDS tH R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 tLOW tHIGH CSB Figure 3. Serial Port Interface Timing Diagram Rev. 0 | Page 8 of 64 |
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