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AD7920BKS-REEL Arkusz danych(PDF) 5 Page - Analog Devices |
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AD7920BKS-REEL Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 20 page REV. B AD7910/AD7920 –5– CS SCLK SDATA t2 t6 t3 t4 t7 t5 t8 tCONVERT tQUIET ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0 B THREE-STATE THREE- STATE Z 4 LEADING ZEROS 12 345 13 14 15 16 t1 Figure 2. AD7920 Serial Interface Timing Diagram CS SCLK t2 tCONVERT B 1 234 5 13 14 15 16 C t8 tQUIET tACQ 12.5(1/fSCLK) 1/THROUGHPUT Figure 3. Serial Interface Timing Example TO OUTPUT PIN CL 50pF 200 A IOH 200 A IOL 1.6V Figure 1. Load Circuit for Digital Output Timing Specifications TIMING EXAMPLES Figures 2 and 3 show some of the timing parameters from the Timing Specifications table. Timing Example 1 From Figure 3, having fSCLK = 5 MHz and a throughput rate of 250 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 ms. With t2 = 10 ns min, this leaves tACQ to be 1.49 ms. This 1.49 ms satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This allows a value of 954 ns for tQUIET, satisfying the minimum re- quirement of 50 ns. Timing Example 2 The AD7920 can also operate with slower clock frequencies. From Figure 3, having fSCLK = 3.4 MHz and a throughput rate of 150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 6.66 ms. With t2 = 10 ns min, this leaves tACQ to be 2.97 ms. This 2.97 ms satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This allows a value of 2.19 ms for tQUIET, satisfying the minimum requirement of 50 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 50 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 3. |
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