AD9230-11

Rev. 0 | Page 9 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

D2–

2

D2+

3

D3–

4

D3+

5

D4–

6

D4+

7

DRVDD

8

DRGND

9

D5–

10

D5+

11

D6–

12

D6+

13

D7–

14

D7+

35 VIN+

36 VIN–

37 AVDD

38 AVDD

39 AVDD

40 CML

41 AVDD

42 AVDD

34 AVDD

33 AVDD

32 AVDD

31 RBIAS

30 AVDD

29 PWDN

TOP VIEW

(Not to Scale)

AD9230-11

NOTES

1. DNC = DO NOT CONNECT.

2. PIN 0 (EXPOSED PADDLE) = AGND.

Figure 4. Single Data Rate Mode Pin Configuration

Table 7. Single Data Rate Mode Pin Function Descriptions

Pin No.

Mnemonic

Description

30, 32 to 34, 37 to 39, 41 to

43, 46

AVDD

1.8 V Analog Supply.

7, 24, 47

DRVDD

1.8 V Digital Output Supply.

0

AGND1

Analog Ground. The exposed paddle should be connected to the analog ground.

8, 23, 48

DRGND1

Digital Output Ground.

35

VIN+

Analog Input (True).

36

VIN−

Analog Input (Complement).

40

CML

Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−.

44

CLK+

Clock Input (True).

45

CLK−

Clock Input (Complement).

31

RBIAS

Set Pin for Chip Bias Current. Place 1% 10 kΩ resistor terminated to ground. Nominally 0.5 V.

28

RESET

CMOS-Compatible Chip Reset (Active Low).

25

SDIO/DCS

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Duty Cycle Stabilizer Select

(External Pin Mode).

26

SCLK/DFS

Serial Port Interface Clock (Serial Port Mode). Data Format Select Pin (External Pin Mode).

27

CSB

Serial Port Chip Select (Active Low).

29

PWDN

Chip Power-Down.

49

DCO−

Data Clock Output (Complement).

50

DCO+

Data Clock Output Input (True).

51, 52

DNC

Do No Connect.

53

D0− (LSB)

D0 Complement Output Bit (LSB).

54

D0+ (LSB)

D0 True Output Bit (LSB).

55

D1−

D1 Complement Output Bit.

56

D1+

D1 True Output Bit.

1

D2−

D2 Complement Output Bit.

2

D2+

D2 True Output Bit.