AD9248BCPZRL-40 datasheet(11/49 Pages) AD

Numer części	AD9248BCPZRL-40

Szczegółowy opis	Dual A/D Converter

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AD9248

Rev. B | Page 10 of 48

Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 4, 13, 16

AGND

Analog Ground.

2

VIN+_A

Analog Input Pin (+) for Channel A.

3

VIN−_A

Analog Input Pin (−) for Channel A.

5, 12, 17, 64

AVDD

Analog Power Supply.

6

REFT_A

Differential Reference (+) for Channel A.

7

REFB_A

Differential Reference (−) for Channel A.

8

VREF

Voltage Reference Input/Output.

9

SENSE

Reference Mode Selection.

10

REFB_B

Differential Reference (−) for Channel B.

11

REFT_B

Differential Reference (+) for Channel B.

14

VIN−_B

Analog Input Pin (−) for Channel B.

15

VIN+_B

Analog Input Pin (+) for Channel B.

18

CLK_B

Clock Input Pin for Channel B.

19

DCS

Enable Duty Cycle Stabilizer (DCS) Mode.

20

DFS

Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement).

21

PDWN_B

Power-Down Function Selection for Channel B.

Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z).

22

OEB_B

Output Enable Pin for Channel B.

Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z.

23 to 27,

30 to 38

D0_B (LSB) to

D13_B (MSB)

Channel B Data Output Bits.

28, 40, 53

DRGND

Digital Output Ground.

29, 41, 52

DRVDD

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.

Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF capacitor.

39

OTR_B

Out-of-Range Indicator for Channel B.

42 to 51,

54 to 57

D0_A (LSB) to

D13_A (MSB)

Channel A Data Output Bits.

58

OTR_A

Out-of-Range Indicator for Channel A.

59

OEB_A

Output Enable Pin for Channel A.

Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z.

60

PDWN_A

Power-Down Function Selection for Channel A.

Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z).

61

MUX_SELECT

Data Multiplexed Mode.

(See Data Format section for how to enable; high setting disables output data multiplexed mode.)

62

SHARED_REF

Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode).

63

CLK_A

Clock Input Pin for Channel A.

EP

For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.

Podobny numer części - AD9248BCPZRL-40

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Analog Devices	AD9248BCPZRL-40	1Mb / 48P	14-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter REV. B

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