ADAU1702 datasheet(6/53 Pages) AD

Numer części	ADAU1702

Szczegółowy opis	SigmaDSP 28-/56-Bit Audio Processor

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Data Sheet

ADAU1702

Rev. D | Page 5 of 52

SPECIFICATIONS

AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted.

ANALOG PERFORMANCE

Specifications are guaranteed at 25°C (ambient).

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC INPUTS

Number of Channels

2

Stereo input

Resolution

24

Bits

Full-Scale Input

100 (283)

µA rms (µA p-p)

2 V rms input with 20 kΩ (18 kΩ external + 2 kΩ

internal) series resistor

Signal-to-Noise Ratio

A-Weighted

100

dB

Dynamic Range

−60 dB with respect to full-scale analog input

A-Weighted

95

100

dB

Total Harmonic Distortion + Noise

−83

dB

−3 dB with respect to full-scale analog input

Interchannel Gain Mismatch

25

250

mdB

Crosstalk

−82

dB

Analog channel-to-channel crosstalk

DC Bias

1.4

1.5

1.6

V

Gain Error

−11

+11

%

Group Delay

480

µs

Delay is the same across all frequencies

DAC OUTPUTS

Number of Channels

4

Two stereo output channels

Resolution

24

Bits

Full-Scale Analog Output

0.9 (2.5)

V rms (V p-p)

Signal-to-Noise Ratio

A-Weighted

104

dB

Dynamic Range

−60 dB with respect to full-scale analog output

A-Weighted

99

104

dB

Total Harmonic Distortion + Noise

−90

dB

−1 dB with respect to full-scale analog output

Crosstalk

−100

dB

Analog channel-to-channel crosstalk

Interchannel Gain Mismatch

25

250

mdB

Gain Error

−10

+10

%

DC Bias

1.4

1.5

1.6

V

Group Delay

400

µs

Delay is the same across all frequencies

VOLTAGE REFERENCE

Absolute Voltage (CM)

1.4

1.5

1.6

V

AUXILIARY ADC

Full-Scale Analog Input

2.8

3.0

3.1

V

INL

0.5

LSB

DNL

1.0

LSB

Offset

15

mV

Input Impedance

17.8

30

42

kΩ

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