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ADAU1777BCBZRL Arkusz danych(PDF) 11 Page - Analog Devices

Numer części ADAU1777BCBZRL
Szczegółowy opis  Four-ADC, Two-DAC, Low Power Codec
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ADAU1777BCBZRL Arkusz danych(HTML) 11 Page - Analog Devices

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ADAU1777
Data Sheet
Rev. 0 | Page 10 of 108
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V.
Table 7. Digital Timing
Limit
Parameter
tMIN
tMAX
Unit
Description
MASTER CLOCK (MCLK)
tMP
37
125
ns
MCLKIN period; 8 MHz to 27 MHz input clock using PLL
tMCLK
77
82
ns
Internal MCLK period; direct MCLK and PLL output divided by 2
SERIAL PORT
tBL
40
ns
BCLK low pulse width (master and slave modes)
tBH
40
ns
BCLK high pulse width (master and slave modes)
tLS
10
ns
LRCLK setup; time to BCLK rising (slave mode)
tLH
10
ns
LRCLK hold; time from BCLK rising (slave mode)
tSS
5
ns
DAC_SDATA setup; time to BCLK rising (master and slave modes)
tSH
5
ns
DAC_SDATA hold; time from BCLK rising (master and slave modes)
tTS
10
ns
BCLK falling to LRCLK timing skew (master mode)
tSOD
0
34
ns
ADC_SDATAx delay; time from BCLK falling (master and slave modes)
tSOTD
30
ns
BCLK falling to ADC_SDATAx driven in time-division multiplexing
(TDM) tristate mode
tSOTX
30
ns
BCLK falling to ADC_SDATAx tristate in TDM tristate mode
SERIRAL PERIPHERAL INTERFACE
(SPI) PORT
fSCLK
6.25
MHz
SCLK frequency
tCCPL
80
ns
SCLK pulse width low
tCCPH
80
ns
SCLK pulse width high
tCLS
5
ns
SS setup; time to SCLK rising
tCLH
100
ns
SS hold; time from SCLK rising
tCLPH
80
ns
SS pulse width high
tCDS
10
ns
MOSI setup; time to SCLK rising
tCDH
10
ns
MOSI hold; time from SCLK rising
tCOD
101
ns
MISO delay; time from SCLK falling
I2C PORT
fSCL
400
kHz
SCL frequency
tSCLH
0.6
µs
SCL high
tSCLL
1.3
µs
SCL low
tSCS
0.6
µs
SCL rise setup time (to SDA falling), relevant for repeated start
condition
tSCR
250
ns
SCL and SDA rise time, CLOAD = 400 pF
tSCH
0.6
µs
SCL fall hold time (from SDA falling), relevant for start condition
tDS
100
ns
SDA setup time (to SCL rising)
tSCF
250
ns
SCL and SDA fall time; CLOAD = 400 pF
tBFT
0.6
µs
SCL rise setup time (to SDA rising), relevant for stop condition
I2C EEPROM SELF BOOT
tSCHE
26 × tMP − 70
ns
SCL fall hold time (from SDA falling), relevant for start condition; tMP
is the input clock on the MCLKIN pin
tSCSE
38 × tMP − 70
ns
SCL rise setup time (to SDA falling), relevant for repeated start
condition
tBFTE
70 × tMP − 70
ns
SCL rise setup time (to SDA rising), relevant for stop condition
tDSE
6 × tMP − 70
ns
Delay from SCL falling to SDA changing
tBHTE
32 × tMP
ns
SDA rising in self boot stop condition to SDA falling edge for
external master start condition


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