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TLA2024IRUGR Arkusz danych(PDF) 6 Page - Texas Instruments |
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TLA2024IRUGR Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 33 page tBUF tLOW 1 / fSCL 1 st clock cycle tSU;STA tHD;STA Sr 9 th clock tVD;ACK 70% 30% tSU;STO P S 70% 30% 9 th clock tHD;STA S 70% 30% SDA SCL tf tr tf tHD;DAT tr tSU;DAT 70% 30% tVD;DAT tHIGH . . . cont. . . . cont. SDA SCL 6 TLA2021, TLA2022, TLA2024 SBAS846 – NOVEMBER 2017 www.ti.com Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.6 I 2C Timing Requirements over operating ambient temperature range and VDD = 2 V to 5.5 V (unless otherwise noted) MIN MAX UNIT STANDARD-MODE fSCL SCL clock frequency 10 100 kHz tLOW Pulse duration, SCL low 4.7 µs tHIGH Pulse duration, SCL high 4.0 µs tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 4 µs tSU;STA Setup time, repeated START condition 4.7 µs tHD;DAT Hold time, data 0 µs tSU;DAT Setup time, data 250 ns tr Rise time, SCL, SDA 1000 ns tf Fall time, SCL, SDA 250 ns tSU;STO Setup time, STOP condition 4.0 µs tBUF Bus free time, between STOP and START condition 4.7 µs tVD;DAT Valid time, data 3.45 µs tVD;ACK Valid time, acknowledge 3.45 µs FAST-MODE fSCL SCL clock frequency 10 400 kHz tLOW Pulse duration, SCL low 1.3 µs tHIGH Pulse duration, SCL high 0.6 µs tHD;STA Hold time, (repeated) START condition. After this period, the first clock pulse is generated. 0.6 µs tSU;STA Setup time, repeated START condition 0.6 µs tHD;DAT Hold time, data 0 µs tSU;DAT Setup time, data 100 ns tr Rise time, SCL, SDA 20 300 ns tf Fall time, SCL, SDA 300 ns tSU;STO Setup time, STOP condition 0.6 µs tBUF Bus free time, between STOP and START condition 1.3 µs tVD;DAT Valid time, data 0.9 µs tVD;ACK Valid time, acknowledge 0.9 µs Figure 1. I2C Timing Requirements |
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