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ST92F120JR1Q7 Arkusz danych(PDF) 1 Page - STMicroelectronics

Numer części ST92F120JR1Q7
Szczegółowy opis  8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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September 2002
1/324
Rev. 2.6
ST92F120
8/16-BIT FLASH MCU FAMILY
WITH RAM, EEPROM AND J1850 BLPD
DATASHEET
s
Memories
– Internal Memory: up to 128 Kbytes Single
Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte
emulated EEPROM (E3PROMTM)
– 224 general purpose registers (register file)
available as RAM, accumulators or index
pointers
s
Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN,
WFI, SLOW, HALT and STOP modes
– 0-24 MHz Operation (internal Clock), 4.5 - 5.5
Volt voltage range
– PLL Clock Generator (3-5 MHz crystal)
– Min. instruction time: 83 ns (24 MHz int.
clock)
s
Interrupt Management
– 77 I/O pins
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or
additional external interrupt with multi-level in-
terrupt handler
s
Timers
– 16-bit Timer with 8 bit Prescaler, able to be
used as a Watchdog Timer with a large range
of service time (HW/SW enabling through
dedicated pin)
– 16-bit Standard Timer that can be used to
generate a time base independent of PLL
Clock Generator
– Two 16-bit independent Extended Function
Timers (EFTs) with Prescaler, 2 Input Cap-
tures and two Output Compares
– Two 16-bit Multifunction Timers, with Prescal-
er, 2 Input Captures and 2 Output Compares
s
Communication Interfaces
– 2 Serial Communication Interfaces with asyn-
chronous and synchronous capabilities. Soft-
ware Management and synchronous mode
supported
– Serial Peripheral Interface (SPI) with Selecta-
ble Master/Slave mode
– J1850 Byte Level Protocol Decoder (JBLPD)
(on J versions only)
– Full I²C multiple Master/Slave Interface sup-
porting Access Bus
s
8-bit Analog to Digital Converter allowing up
to 16 input channels
s
DMA
Controller
for
reduced
processor
overhead
s
Instruction Set
– Rich Instruction Set with 14 Addressing
Modes
– Division-by-zero trap generation
s
Development Tools
– Versatile Development Tools, including As-
sembler,
Linker,
C-Compiler,
Archiver,
Source Level Debugger, Hardware Emulators
and Real Time Operating System
DEVICE SUMMARY
PQFP100
Features
ST92F120V9
ST92F120JV9
ST92F120V1
ST92F120JV1
FLASH - bytes
60K
128K
RAM - bytes
2K
4K
E3PROM - bytes
1K
Network Interface
--
J1850
--
J1850
Temp. Range
-40o C to 105o C or -40oC to 85o C
Packages
PQFP100
9


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