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AD7150 Arkusz danych(PDF) 9 Page - Analog Devices |
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AD7150 Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 29 page AD7150 Rev. 0 | Page 8 of 28 500 –500 –250 0 250 11000 100 10 RESISTANCE CIN TO GND (MΩ) Figure 10. Capacitance Input Offset Error vs. Resistance CIN to GND, VDD = 3.3 V, EXC Pin Open Circuit 10 –10 –5 0 5 11000 100 10 RESISTANCE CIN TO GND (MΩ) 8 6 4 2 RESISTANCE EXC TO GND (MΩ) Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND, VDD = 3.3 V, CIN to EXC = 2 pF 10 –10 –5 0 5 010 0.50 –0.50 –0.25 0 0.25 010 8 6 4 2 RESISTANCE EXC TO GND (MΩ) 2 –8 –6 –4 –2 0 0250 200 150 100 50 SERIAL RESISTANCE (kΩ) Figure 12. Capacitance Input Offset Error vs. Resistance EXC to GND, VDD = 3.3 V, CIN Pin Open Circuit Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND, VDD = 3.3 V, CIN to EXC = 2 pF Figure 14. Capacitance Input Gain Error vs. Serial Resistance, VDD = 3.3 V, CIN to EXC = 2 pF 10 –10 –5 0 5 11000 100 10 PARALLEL RESISTANCE (MΩ) Figure 15. Capacitance Input Gain Error vs. Parallel Resistance, VDD = 3.3 V, CIN to EXC = 2 pF |
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