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AD73322 Arkusz danych(PDF) 16 Page - Analog Devices |
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AD73322 Arkusz danych(HTML) 16 Page - Analog Devices |
16 / 44 page AD73322 –15– REV. B ADC Both ADCs consist of an analog sigma-delta modulator and a digital antialiasing decimation filter. The sigma-delta modu- lator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution. Analog Sigma-Delta Modulator The AD73322’s input channels employ a sigma-delta conver- sion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73322, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to FS/2 = DMCLK/16 (Figure 10a). This means that the noise in the band of interest is much reduced. Another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. This technique has the effect of pushing the noise from the band of interest to an out-of-band position (Figure 10b). The combi- nation of these techniques, followed by the application of a digital filter, sufficiently reduces the noise in band to ensure good dynamic performance from the part (Figure 10c). BAND OF INTEREST FS/2 DMCLK/16 FS/2 DMCLK/16 FS/2 DMCLK/16 DIGITAL FILTER NOISE SHAPING BAND OF INTEREST BAND OF INTEREST a. b. c. Figure 10. Sigma-Delta Noise Reduction Figure 11 shows the various stages of filtering that are employed in a typical AD73322 application. In Figure 11a we see the transfer function of the external analog antialias filter. Even though it is a single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency. This also shows the major difference between the initial oversampling rate and the bandwidth of interest. In Fig- ure 11b, the signal and noise-shaping responses of the sigma- delta modulator are shown. The signal response provides further rejection of any high frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. The detail of Figure 11c shows the response of the digital decimation filter (Sinc-cubed response) with nulls every multiple of DMCLK/256, which corresponds to the decimation filter update rate for a 64 kHz sampling. The nulls of the Sinc3 response correspond with multiples of the chosen sampling frequency. The final detail in Figure 11d shows the application of a final antialias filter in the DSP engine. This has the advan- tage of being implemented according to the user’s requirements and available MIPS. The filtering in Figures 11a through 11c is implemented in the AD73322. FB = 4kHz FSINIT = DMCLK/8 a. Analog Antialias Filter Transfer Function FB = 4kHz FSINIT = DMCLK/8 NOISE TRANSFER FUNCTION SIGNAL TRANSFER FUNCTION b. Analog Sigma-Delta Modulator Transfer Function FB = 4kHz FSINTER = DMCLK/256 c. Digital Decimator Transfer Function FB = 4kHz FSINTER = DMCLK/256 FSFINAL = 8kHz d. Final Filter LPF (HPF) Transfer Function Figure 11. ADC Frequency Responses |
Podobny numer części - AD73322_17 |
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Podobny opis - AD73322_17 |
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