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AD73322 Arkusz danych(PDF) 25 Page - Analog Devices |
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AD73322 Arkusz danych(HTML) 25 Page - Analog Devices |
25 / 44 page AD73322 –24– REV. B OPERATION Resetting the AD73322 The RESET pin resets all the control registers. All registers are reset to zero, indicating that the default SCLK rate (DMCLK/ 8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed DSP engines can communicate effectively. As well as resetting the control registers using the RESET pin, the device can be reset using the RESET bit (CRA:7) in Control Register A. Both hardware and software resets require four DMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0 (default condition) thus enabling Program Mode. The reset conditions ensure that the device must be programmed to the correct settings after power-up or reset. Following a reset, the SDOFS will be asserted 2048 DMCLK cycles after RESET going high. The data that is output following reset and during Program Mode is random and contains no valid information until either data or mixed mode is set. Power Management The individual functional blocks of the AD73322 can be en- abled separately by programming the power control register CRC. It allows certain sections to be powered down if not re- quired, which adds to the device’s flexibility in that the user need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. The power control registers provide individual control settings for the major functional blocks on each codec unit and also a global override that allows all sections to be powered up by setting the bit. Using this method the user could, for example, individually enable a certain section, such as the reference (CRC:5), and disable all others. The global power-up (CRC:0) can be used to enable all sections, but if power-down is required using the global control, the reference will still be enabled, in this case, because its individual bit is set. Refer to Table XVI for details of the settings of CRC. NOTE: As both codec units share a common reference, the reference control bits (CRC:5-7) in each SPORT are wire ORed to allow either device to control the reference. Operating Modes There are three main modes of operation available on the AD73322; Program, Data and Mixed Program/Data modes. Two other operating modes are typically reserved as diagnostic modes: Digital and SPORT Loop-Back. The device configuration— register settings—can be changed only in Program and Mixed Program/Data Modes. In all modes, transfers of information to or from the device occur in 16-bit packets, therefore the DSP engine’s SPORT will be programmed for 16-bit transfers. Program (Control) Mode In Program Mode, CRA:0 = 0, the user writes to the control registers to set up the device for desired operation—SPORT operation, cascade length, power management, input/output gain, etc. In this mode, the 16-bit information packet sent to the device by the DSP engine is interpreted as a control word whose format is shown in Table XIII. In this mode, the user must address the device to be programmed using the address field of the control word. This field is read by the device and if it is zero (000 bin), the device recognizes the word as being addressed to it. If the address field is not zero, it is then decremented and the control word is passed out of the device—either to the next device in a cascade or back to the DSP engine. This 3-bit address format allows the user to uniquely address any one of up to eight devices in a cascade; please note that this addressing scheme is valid only in sending control information to the device —a different format is used to send DAC data to the device(s). As the AD73322 is a dual codec, it features two separate device addresses for programming purposes. If the AD73322 is used in a standalone configuration connected to a DSP, the two device addresses correspond to 0 and 1. If, on the other hand, the AD73322 is configured in a cascade of multiple, dual or single codecs (AD73322 or AD73311), its device addresses corre- spond with its hardwired position in the cascade. Following reset, when the SE pin is enabled, the codec responds by raising the SDOFS pin to indicate that an output sample event has occurred. Control words can be written to the device to coincide with the data being sent out of the SPORT, as shown in Figure 15, or they can lag the output words by a time interval that should not exceed the sample interval. After reset, output frame sync pulses will occur at a slower default sample rate, which is DMCLK/2048, until Control Register B is programmed, after which the SDOFS pulses will be set ac- cording to the contents of DIR0-1. This is to allow slow con- troller devices to establish communication with the AD73322. During Program Mode, the data output by the device is random and should not be interpreted as ADC data. SAMPLE WORD (DEVICE 2) SE SDOFS SCLK SDO SDIFS SDI SAMPLE WORD (DEVICE 1) CONTROL WORD (DEVICE 2) CONTROL WORD (DEVICE 1) Figure 15. Interface Signal Timing for Control Mode Operation Data Mode Once the device has been configured by programming the cor- rect settings to the various control registers, the device may exit Program Mode and enter Data Mode. This is done by program- ming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to 0. Once the device is in Data Mode, the 16-bit input data frame is now interpreted as DAC data rather than a control frame. This data is therefore loaded directly to the DAC register. In Data Mode, see Figure 16, as the entire input data frame con- tains DAC data, the device relies on counting the number of input frame syncs received at the SDIFS pin. When that num- ber equals the device count stored in the device count field of CRA, the device knows that the present data frame being re- ceived is its own DAC update data. When the device is in nor- mal Data Mode (i.e., mixed mode disabled), it must receive a hardware reset to reprogram any of the control register settings. |
Podobny numer części - AD73322_17 |
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Podobny opis - AD73322_17 |
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