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AD7877WACPZ-REEL7 Arkusz danych(PDF) 6 Page - Analog Devices |
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AD7877WACPZ-REEL7 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 46 page Data Sheet AD7877 TIMING SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted, VCC = 2.7 V to 5.25 V, VREF = 2.5 V. Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. Table 2. Parameter Limit at TMIN, TMAX Unit Description fDCLK1 10 kHz min 20 MHz max t1 16 ns min CS falling edge to first DCLK rising edge t2 20 ns min DCLK high pulse width t3 20 ns min DCLK low pulse width t4 12 ns min DIN setup time t5 12 ns min DIN hold time t62 16 ns max CS falling edge to DOUT, three-state disabled t72 16 ns max DCLK falling edge to DOUT valid t83 16 ns max CS rising edge to DOUT high impedance t9 0 ns min CS rising edge to DCLK ignored 1 Mark/space ratio for the DCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V. 3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. TIMING DIAGRAMS DCLK t1 t2 t3 t5 t4 t6 t7 t9 t8 DIN MSB LSB MSB LSB DOUT 1 2 3 15 16 CS Figure 2. Detailed Timing Diagram 200 µA IOL 200 µA IOH 1.6V TO OUTPUT PIN CL 50pF Figure 3. Load Circuit for Digital Output Timing Specifications Rev. E | Page 5 of 45 |
Podobny numer części - AD7877WACPZ-REEL7 |
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Podobny opis - AD7877WACPZ-REEL7 |
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