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ADE9000ACPZ-RL Arkusz danych(PDF) 9 Page - Analog Devices |
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ADE9000ACPZ-RL Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 73 page ADE9000 Data Sheet Rev. A | Page 8 of 72 Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY VDD 2.97 3.3 3.63 V Power-on reset level is 2.4 V to 2.6 V Supply Current (VDD) Power Save Mode 0 (PSM0) 15 17 mA Normal mode 14.5 16.5 mA Normal mode, six ADCs enabled Power Save Mode 3 (PSM3) 90 300 nA Idle, VDD = 3.3 V, AVDD = 0 V, DVDD = 0 V 1 Enables implementation of IEC 61000-4-30 Class S. 2 Tested during device characterization. TIMING CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit SS to SCLK Edge tSS 10 ns SCLK Frequency fSCLK 20 MHz SCLK Low Pulse Width tSL 20 ns SCLK High Pulse Width tSH 20 ns Data Output Valid After SCLK Edge tDAV 20 ns Data Input Setup Time Before SCLK Edge tDSU 10 ns Data Input Hold Time After SCLK Edge tDHD 10 ns Data Output Fall Time tDF 10 ns Data Output Rise Time tDR 10 ns SCLK Fall Time tSF 10 ns SCLK Rise Time tSR 10 ns MISO Disable Time After SS Rising Edge tDIS 100 ns SS High After SCLK Edge tSFS 0 ns MSB LSB LSB IN INTERMEDIATE BITS INTERMEDIATE BITS tSFS tDIS tSS tSL tDF tSH tDHD tDAV tDSU tSR tSF tDR MSB IN MOSI MISO SCLK SS Figure 2. SPI Interface Timing Digram |
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