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ADT7410TRZ Arkusz danych(PDF) 5 Page - Analog Devices |
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ADT7410TRZ Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 25 page ADT7410 Data Sheet Rev. C | Page 4 of 24 I2C TIMING SPECIFICATIONS TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SERIAL INTERFACE1, 2 See Figure 2 SCL Frequency 0 400 kHz SCL High Pulse Width, tHIGH 0.6 µs SCL Low Pulse Width, tLOW 1.3 µs SCL, SDA Rise Time, tR 0.3 µs SCL, SDA Fall Time, tF 0.3 µs Hold Time (Start Condition), tHD;STA 0.6 µs After this period, the first clock is generated Setup Time (Start Condition), tSU;STA 0.6 µs Relevant for repeated start condition Data Setup Time, tSU;DAT 0.25 µs VDD ≥ 3.0 V 0.35 µs VDD < 3.0 V Setup Time (Stop Condition), tSU;STO 0.6 µs Data Hold Time, tHD;DAT (Master) 0 µs Bus-Free Time (Between Stop and Start Condition), tBUF 1.3 µs 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. Timing Diagram P S tLOW tR tF tHD:STA tHD:DAT tSU:DAT tSU:STA tHD:STA tSU:STO tHIGH SCL P S SDA tBUF Figure 2. Serial Interface Timing Diagram |
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