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AD6657ABBCZRL Arkusz danych(PDF) 11 Page - Analog Devices |
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AD6657ABBCZRL Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 37 page AD6657A Data Sheet TIMING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 5. Parameter Description Min Typ Max Unit SYNC TIMING REQUIREMENTS See Figure 3 for details tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS See Figure 60 for details, except where noted tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not pictured in Figure 60) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not pictured in Figure 60) 10 ns Sync Input Timing Diagram Figure 3. SYNC Input Timing Requirements SYNC CLK+ tHSYNC tSSYNC Rev. A | Page 10 of 36 |
Podobny numer części - AD6657ABBCZRL |
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Podobny opis - AD6657ABBCZRL |
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