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AD6673BCPZ-250 Arkusz danych(PDF) 1 Page - Analog Devices |
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AD6673BCPZ-250 Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 46 page 80 MHz Bandwidth, Dual IF Receiver Data Sheet AD6673 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and 250 MSPS with NSR set to 33% Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS Total power consumption: 707 mW at 250 MSPS 1.8 V supply voltages Integer 1-to-8 input clock divider Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz Internal analog-to-digital converter (ADC) voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) 95 dB channel isolation/crosstalk Serial port control Energy saving power-down modes APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems General-purpose software radios FUNCTIONAL BLOCK DIAGRAM CML, TX OUTPUTS JESD-204B INTERFACE HIGH SPEED SERIALIZERS PIPELINE 11-BIT ADC PIPELINE 11-BIT ADC CMOS DIGITAL INPUT CMOS DIGITAL OUTPUT FAST DETECT CONTROL REGISTERS CLOCK GENERATION AVDD VIN+A SDIO SCLK FDB FDA PDWN SERDOUT1± SERDOUT0± CS VIN–A VIN+B VCM VIN–B SYSREF± SYNCINB± CLK± RFCLK DRVDD AGND CMOS DIGITAL INPUT/OUTPUT DRGND RST AD6673 DVDD DGND NSR NSR Figure 1. PRODUCT HIGHLIGHTS 1. The configurable JESD204B output block with an integrated phase-locked loop (PLL) to support up to 5 Gbps per lane with up to two lanes. 2. IF receiver includes two, 11-bit, 250 MSPS ADCs with programmable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of 22% or 33% of the sample rate. 3. Support for an optional RF clock input to ease system board design. 4. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. 5. An on-chip integer, 1-to-8 input clock divider and SYNC input allows synchronization of multiple devices. 6. Operation from a single 1.8 V power supply. 7. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration. This product may be protected by one or more U.S. or international patents. |
Podobny numer części - AD6673BCPZ-250 |
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Podobny opis - AD6673BCPZ-250 |
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