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TC94A04AFD Arkusz danych(PDF) 11 Page - Toshiba Semiconductor |
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TC94A04AFD Arkusz danych(HTML) 11 Page - Toshiba Semiconductor |
11 / 42 page TC94A04AF/AFD 2001-11-15 11 2.2 I 2 C Bus Mode When I2CS = “H”, data can be transmitted or received in I2C bus mode. When the CS signal is Low, control from the microcontroller is enabled. In I2C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock. The IFDI signal is the data. The TC94A04AF/AFD loads the IFDI data on the IFCK signal rising edge. When CS = “H”, IFCK and IFD signal are don't care. 2.2.1 Setting Registers The registers are set by command data using the IFDI signal. The first byte after the I2C address (= 32h) is a command, which differs for each register. The data sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C format. The data loaded internally every two bytes. Note that commands or data that must be switched on the SYNC signal, such as the RUN command (command-44h) or the IFF flag (command-4Ah), must be synchronized with the SYNC signal and loaded on that signal. CS IFDI IFCK C3 C2 C5 C4 C7 C6 C1 C0 A3 A2 A5 A4 A7 A6 A1 A0 D11 D10 D13 D12 D15 D14 D9 D8 An: I 2 C address Cn: COMMAND Dn: Data (MCU →) start 32h HZ HZ HZ HZ end D3 D2 D5 D4 D7 D6 D1 65 |
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