Data Sheet

AD7262

Rev. B | Page 9 of 32

Pin No.

Mnemonic

Description

23

Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction

with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts

as the data input pin, and all programming is via the control register (see Table 8). Data to be written

to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register

on the falling edge of SCLK.

35

CS

Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5.

48, 47, 46, 45

Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A

and Comparator B. These two comparators have very low power consumption.

13, 14, 15, 16

Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C

and Comparator D. This pair of comparators offers very fast propagation delays.

5, 6, 8, 19, 42

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. Refer all

analog input signals and any external reference signal to this AGND voltage. All AGND pins should

ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient

28

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5.

Connect the DGND pin to the DGND plane of a system. The DGND and AGND voltages should

ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

30, 29, 26, 25

Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective

32, 31

Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial

data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK

input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During

the conversion process, the data output pins are in three-state and, when the conversion is

from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for

40, 39, 38, 37

G0, G1, G2, G3

Logic Inputs. These pins program the gain setting of the front-end amplifiers. If all four pins are tied

(see Table 6).

27

Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what

voltage the interface operates, including the comparator outputs. Decouple this pin to DGND.

44, 17

Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/

ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

24

REFSEL

Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on-

chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is

EPAD

Exposed Metal Paddle. The exposed metal paddle on the bottom of the LFCSP package must be

soldered to PCB ground for proper heat dissipation and also for noise and mechanical strength

benefits.