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MT9M131 Arkusz danych(PDF) 48 Page - ON Semiconductor |
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MT9M131 Arkusz danych(HTML) 48 Page - ON Semiconductor |
48 / 50 page MT9M131 www.onsemi.com 48 Table 23. TWO-WIRE SERIAL INTERFACE TIMING (VDD =VAA =VAA_PIX = VDD_IO = 2.8 V, TA = −30°C to +70°C) Symbol Definition Min Typ Max Unit fIC Two-wire Serial Bus Input Clock Frequency – – 400 KHz tIC Two-wire Serial Bus Input Clock Period 2500 – – ns tICL Two-wire Serial Bus Clock LOW – 1250 – ns tICH Two-wire Serial Bus Clock HIGH – 1250 – ns tISS Setup Time for Start Condition 600 – – ns tIHS Hold Time for Start Condition 600 – – ns tISD Setup Time for Input Data 600 – – ns tIHD Hold Time for Input Data 600 – – ns tOAA Output Delay Time – – 600 ns tISP Setup Time of Stop Condit ion 600 – – ns tIHP Hold Time for Stop Condition 600 – – ns CSCLCK/SDATA SCLCK and SDATA Load Capacitance – – 30 pF RSCLCK/SDATA SCLCK and SDATA Pull-up Resistor – 1.5 – k W NOTE: A minimum EXTCLK frequency of 4 MHz is required for the two-wire serial interface to operate at 400 kHz. |
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