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AD9925 Arkusz danych(PDF) 3 Page - Analog Devices |
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AD9925 Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 96 page AD9925 Rev. A | Page 3 of 96 SPECIFICATIONS Table 1. Parameter Min Typ Max Unit TEMPERATURE RANGE Operating –25 +85 °C Storage –65 +150 °C POWER SUPPLY VOLTAGES AVDD (AFE Analog Supply) 2.7 3.0 3.6 V TCVDD (Timing Core Analog Supply) 2.7 3.0 3.6 V RGVDD (RG Driver) 2.7 3.0 3.6 V HVDD (H1 to H4 Drivers) 2.7 3.0 3.6 V DRVDD (Data Output Drivers) 2.7 3.0 3.6 V DVDD (Digital) 2.7 3.0 3.6 V V-DRIVER SUPPLY VOLTAGES VDVDD (V-Driver Input Logic Supply) 2.7 3.0 3.6 V VH1, VH2 (V-Driver High Supply for 3-Level Outputs) 10.5 15.0 16.0 V VM1, VM2 (V-Driver Mid Supply for 3-Level and 2-Level Outputs) –1.0 0.0 +3.0 V VL1, VL2 (V-Driver Low Supply for 3-Level and 2-Level Outputs) –10.0 –7.5 –6.0 V POWER DISSIPATION—AFETG Section Only (see Figure 9 for Power Curves) 36 MHz, 3.0 V Supply, 100 pF Load on Each H1 to H4 Output, 20 pF RG Load 370 mW Standby 1 Mode 10 mW Standby 2 Mode 10 mW Standby 3 Mode 1 mW Power from HVDD Only1 130 mW Power from RGVDD Only 10 mW Power from AVDD Only 105 mW Power from TCVDD Only 42 mW Power from DVDD Only 57 mW Power from DRVDD Only 26 mW POWER DISSIPATION—V-Driver Section Only (VDVDD, VH, VL) Normal Operation (VH = 15.0 V, VL = −7.5 V)2 60 mW Standby 1 Mode2 70 mW Standby 2 Mode2 70 mW Standby 3 Mode2 110 mW MAXIMUM CLOCK RATE (CLI) 36 MHz 2 The power dissipated by the V-driver circuitry depends on the logic states of the inputs as well as actual CCD operation; default dc values are used for each measure- ment, in each mode of operation. Load conditions are described in the section. 1 The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD. Reducing the H-loading and/or using a lower HVDD supply will reduce the power dissipation. CLOAD is the total capacitance seen by all H-outputs. Vertical Driver Specifications |
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