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ADS5500 Arkusz danych(PDF) 7 Page - Burr-Brown (TI) |
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ADS5500 Arkusz danych(HTML) 7 Page - Burr-Brown (TI) |
7 / 30 page ADS5542 SBAS308A − MAY 2004 − REVISED MARCH 2005 www.ti.com 7 RESET TIMING CHARACTERISTICS Typical values at TA = +25 °C, full temperature range is TMIN = −40°C to TMAX = +85°C, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted. PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification Power-on delay, t1 Delay from power−on of AVDD and DRVDD to RESET pulse active 10 ms Reset pulse width, t2 Pulse width of active RESET signal 2 µs Register write delay, t3 Delay from RESET disable to SEN active 2 µs RESET (Pin 35) t1 ≥ 10ms t2 ≥ 2µst3 ≥ 2µs SEN Active Power Supply (AVDD, DRVDD) Figure 2. Reset Timing Diagram SERIAL PROGRAMMING INTERFACE CHARACTERISTICS The device has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of serial clock SCLK when SEN is active. D Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at falling edge. D Minimum width of data stream for a valid loading is 16 clocks. D Data is loaded at every 16th SCLK falling edge while SEN is low. D In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. D Data can be loaded in multiple of 16-bit words within a single active SEN pulse. A3 ADDRESS SDATA MSB DATA A2 A1 A0 D11 D10 D9 D0 Figure 3. DATA Communication is 2-Byte, MSB First |
Podobny numer części - ADS5500 |
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Podobny opis - ADS5500 |
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