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ADT7475 Arkusz danych(PDF) 5 Page - ON Semiconductor |
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ADT7475 Arkusz danych(HTML) 5 Page - ON Semiconductor |
5 / 58 page ADT7475 http://onsemi.com 5 Table 4. ELECTRICAL CHARACTERISTICS (TA =TMIN to TMAX, VCC =VMIN to VMAX, unless otherwise noted.) (Note 1) Parameter Unit Max Typ Min Conditions DIGITAL INPUT CURRENT Input High Current, IIH VIN = VCC − ±1 − mA Input Low Current, IIL VIN = 0 V − ±1 − mA Input Capacitance, CIN − 5 − pF SERIAL BUS TIMING (Note 2) (See Figure 2) Clock Frequency, fSCLK 10 − 400 kHz Glitch Immunity, tSW − − 50 ns Bus Free Time, tBUF 4.7 − − ms SCL Low Time, tLOW 4.7 − − ms SCL High Time, tHIGH 4.0 − 50 ms SCL, SDA Rise Time, tR − − 1,000 ns SCL, SDA Fall Time, tF − − 300 ms Data Setup Time, tSU: DAT 250 − − ns Detect Clock Low Timeout, tTIMEOUT Can be Optionally Disabled 15 − 35 ms 1. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA =25°C and represent the most likely parametric norm. Logic inputs accept input high voltages of up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. 2. SMBus timing specifications are guaranteed by design and are not production tested. Figure 2. Serial Bus Timing Diagram P S tSU; DAT tHIGH tF tHD; DAT tR tLOW tSU; STO PS SCL SDA tBUF tHD; STA tHD; STA tSU; STA |
Podobny numer części - ADT7475 |
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Podobny opis - ADT7475 |
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