Zakładka z wyszukiwarką danych komponentów |
|
AD7683ACPZRL7 Arkusz danych(PDF) 6 Page - Analog Devices |
|
AD7683ACPZRL7 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 17 page Data Sheet AD7683 Rev. B | Page 5 of 16 TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted. Table 5. Parameter Symbol Min Typ Max Unit Throughput Rate tCYC 100 kHz CS Falling to DCLOCK Low tCSD 0 μs CS Falling to DCLOCK Rising tSUCS 20 ns DCLOCK Falling to Data Remains Valid tHDO 5 16 ns CS Rising Edge to DOUT High Impedance tDIS 14 100 ns DCLOCK Falling to Data Valid tEN 16 50 ns Acquisition Time tACQ 400 ns DOUT Fall Time tF 11 25 ns DOUT Rise Time tR 11 25 ns Timing and Circuit Diagrams DOUT DCLOCK COMPLETE CYCLE POWER DOWN CS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) HIGH-Z 0 HIGH-Z tACQ tDIS 0 14 5 tHDO tEN tCSD tSUCS tCYC NOTES 1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING. Figure 2. Serial Interface Timing 500µA IOL 500µA IOH 1.4V TO DOUT CL 100pF Figure 3. Load Circuit for Digital Interface Timing 0.8V 2V 2V 0.8V 0.8V 2V tEN tEN Figure 4. Voltage Reference Levels for Timing DOUT 90% 10% tR tF Figure 5. DOUT Rise and Fall Timing |
Podobny numer części - AD7683ACPZRL7 |
|
Podobny opis - AD7683ACPZRL7 |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |