Data Sheet

AD7938-6

Rev. D | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

NOTES

1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF

THE PACKAGE. CONNECT THE EPAD TO THE GROUND PLANE

OF THE PCB USING MULTIPLE VIAS.

21 AGND

20 CS

19 RD

18 WR

17 CONVST

1

2

3

4

5

6

7

8

AD7938-6

TOP VIEW

(Not to Scale)

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

AGND

21

20

19

WR

18

CONVST

17

AD7938-6

TOP VIEW

(Not to Scale)

RD

CS

PIN 1

IDENTIFIER

Figure 2. Pin Configuration (CP-32-7)

Figure 3. Pin Configuration (SU-32-2)

Table 5. Pin Function Description

Pin No.

Mnemonic

Description

1 to 8

DB0 to DB7

Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the

control and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic

9

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of

the AD7938-6 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that

10

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7938-6. This pin should

connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

11

DB8/HBEN

Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled

by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of

data being written to or read from the AD7938-6 is on DB0 to DB7. When HBEN is high, the top four bits of the

data being written to or read from the AD7938-6 are on DB0 to DB3. When reading from the device, DB4 to DB6

of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel

address bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s.

12 to 14

DB9 to DB11

Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the

control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR.

15

BUSY

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the

falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and

the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode

16

CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the

conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.

17

CONVST

Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from

track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point.

Following power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is

used to power up the device.

18

WR

Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.