Data Sheet

AD7655

Rev. E | Page 9 of 26

Pin No.

Mnemonic

Type1

Description

15

D[6]

DI/O

When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.

or INVSCLK

When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in

both master and slave modes.

16

D[7]

DI/O

When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.

or RDC/SDIN

When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a

read mode selection input, depending on the state of EXT/INT.

When EXT/INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results

from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT

with a delay of 32 SCLK periods after the initiation of the read sequence.

When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the

previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output

on SDOUT only when the conversion is complete.

17

OGND

P

Input/Output Interface Digital Power Ground.

18

OVDD

P

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface

(5 V or 3 V).

19, 36

DVDD

P

Digital Power. Nominally at 5 V.

21

D[8]

DO

When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.

or SDOUT

When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized

to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655 provides the two

conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled

by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.

In serial mode, when EXT/INT is HIGH:

If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.

If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.

22

D[9]

DI/O

When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.

or SCLK

When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,

depends upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated

depends on the logic state of the INVSCLK pin.

23

D[10]

DO

When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.

or SYNC

When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame

synchronization for use with the internal data clock (EXT/INT = Logic LOW).

When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After

the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is

HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is

output, SYNC is pulsed HIGH.

24

D[11]

DO

When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.

or RDERROR

When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an

incomplete read error flag. In slave mode, when a data read is started but not complete when the

following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.

25 to 28

D[12:15]

DO

Bit 12 to Bit 15 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high

impedance.

29

BUSY

DO

Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two

conversions are complete and the data is latched into the on-chip shift register. The falling edge of

BUSY can be used as a data ready clock signal.

30

EOC

DO

End of Convert Output. Goes LOW at each channel conversion.

31

RD

DI

Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.

32

CS

DI

Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is

also used to gate the external serial clock.

33

RESET

DI

Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion, if any, is aborted. If not

used, this pin could be tied to DGND.

34

PD

DI

Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are

inhibited after the current conversion is completed.

35

CNVST

DI

Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and

initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition

phase (t8) is complete, the internal sample-and-hold is put into the hold state and a conversion is

immediately started.