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AD7654 Arkusz danych(PDF) 6 Page - Analog Devices

Numer części AD7654
Szczegółowy opis  16-Bit, 500 kSPS PulSAR Dual, 2-Channel, Simultaneous Sampling ADC
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD7654 Arkusz danych(HTML) 6 Page - Analog Devices

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Data Sheet
AD7654
Rev. D | Page 5 of 27
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
CONVERSION AND RESET (See Figure 23 and Figure 24)
Convert Pulse Width
t1
5
ns
Time Between Conversions
(Normal Mode/Impulse Mode)
t2
2/2.25
μs
CNVST Low to BUSY High Delay
t3
32
ns
BUSY High All Modes Except in Master Serial Read After Convert Mode
(Normal Mode/Impulse Mode)
t4
1.75/2
μs
Aperture Delay
t5
2
ns
End of Conversions to BUSY Low Delay
t6
10
ns
Conversion Time
(Normal Mode/Impulse Mode)
t7
1.75/2
μs
Acquisition Time
t8
250
ns
RESET Pulse Width
t9
10
ns
CNVST Low to EOC High Delay
t10
30
ns
EOC High for Channel A Conversion
(Normal Mode/Impulse Mode)
t11
1/1.25
μs
EOC Low after Channel A Conversion
t12
45
ns
EOC High for Channel B Conversion
t13
0.75
μs
Channel Selection Setup Time
t14
250
ns
Channel Selection Hold Time
t15
30
ns
PARALLEL INTERFACE MODES (See Figure 25 to Figure 29)
CNVST Low to DATA Valid Delay
t16
1.75/2
μs
DATA Valid to BUSY Low Delay
t17
14
ns
Bus Access Request to DATA Valid
t18
40
ns
Bus Relinquish Time
t19
5
15
ns
A/B Low to Data Valid Delay
t20
40
ns
MASTER SERIAL INTERFACE MODES (see Figure 30 and Figure 31)
CS Low to SYNC Valid Delay
t21
10
ns
CS Low to Internal SCLK Valid Delay1
t22
10
ns
CS Low to SDOUT Delay
t23
10
ns
CNVST Low to SYNC Delay (Read During Convert)
(Normal Mode/Impulse Mode)
t24
250/500
ns
SYNC Asserted to SCLK First Edge Delay
t25
3
ns
Internal SCK Period2
t26
23
40
ns
Internal SCLK High2
t27
12
ns
Internal SCLK Low2
t28
7
ns
SDOUT Valid Setup Time2
t29
4
ns
SDOUT Valid Hold Time2
t30
2
ns
SCLK Last Edge to SYNC Delay2
t31
1
ns
CS High to SYNC HI-Z
t32
10
ns
CS High to Internal SCLK HI-Z
t33
10
ns
CS High to SDOUT HI-Z
t34
10
ns
BUSY High in Master Serial Read After Convert2
t35
See Table 4
CNVST Low to SYNC Asserted Delay
(Normal Mode/Impulse Mode)
t36
0.75/1
μs
SYNC Deasserted to BUSY Low Delay
t37
25
ns


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